Keep the SDC information in Yosys's design structures #51
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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@mithro Do you want to review this? |
|
Nope, proceed without me! |
This was referenced Nov 2, 2020
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This PR fixes #45 by modifying the current SDC plugin implementation to not keep the clock and generated clock information in a separate structure, but in Yosys' internal design representation. For this purpose the clock related attributes from this list on the specified wires are set or updated using
create_clocksor as a result of clock propagation.