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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

Popular repositories

  1. chisel3 Public

    Chisel 3: A Modern Hardware Design Language

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  2. Rocket Chip Generator

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  3. verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

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  4. SweRV EH1 core

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  5. firrtl Public

    Flexible Intermediate Representation for RTL

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  6. Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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