Yosys cannot infer BRAM correctly on current master+wip

[mkurc-ant]

Yosys on current master+wip (SHA: 22eaab1) cannot infer BRAM (or any memory) when given a verilog array with a series of initial statements.

I've checked that the last correctly working commit is 98104b3.

In order to reporoduce:

1. Clone the Yosys repo (master+wip branch)
2. Build it
3. Set env. variable YOSYS to point to the Yosys binaty
4. Clode the symbiflow-arch-defs repo (master 2e7d736) and run make env
5. Build EBLIF file for tests/9-soc/picosoc
6. Check how many BRAMS are there in the synthesized design. There should be 2 instead of 1.

I don't know if it is an upstream bug or not so I am posting it here.

[mkurc-ant]

This PR in YosysHQ introduced the unwanted behavior: YosysHQ#843

[mkurc-ant]

Created an issue upstream: YosysHQ#867

[mkurc-ant]

So the problem is now fixed on YosysHQ (f0b2d8e). @litghost Can you integrate master+wip from YosysHQ again? Or at least changes from YosysHQ#868

[litghost]

So the problem is now fixed on YosysHQ (f0b2d8e). @litghost Can you integrate master+wip from YosysHQ again? Or at least changes from YosysHQ#868

I can, but FYI you could have also made the PR.

[mkurc-ant]

@litghost Ok, I've created a PR: #19