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Open source flow for generating bitstreams from Verilog.

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  1. Sphinx Extension which generates various types of diagrams from Verilog code.

    Python 37 16

  2. yosys Public

    Forked from YosysHQ/yosys

    SymbiFlow WIP changes for Yosys Open SYnthesis Suite

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  3. Forked from verilog-to-routing/vtr-verilog-to-routing

    SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

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  4. nextpnr Public

    Forked from YosysHQ/nextpnr

    nextpnr portable FPGA place and route tool

    C++ 19 2

  5. Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

    Python 18 7

  6. Testing Ibex build using Yosys and open source toolchains.

    Shell 11 4


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