Open source flow for generating bitstreams from Verilog.

Pinned repositories

  1. ideas

    Random ideas and interesting ideas for things we hope to eventually do.

    8 1

  2. prjxray

    Documenting the Xilinx 7-series bit-stream format.

    Verilog 168 19

  3. prjxray-db

    Project X-Ray Database: XC7 Series

    Shell 19 2

  4. symbiflow-arch-defs

    FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

    Python 28 20

  5. vtr-verilog-to-routing

    Forked from verilog-to-routing/vtr-verilog-to-routing

    SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C 4 1

  6. yosys

    Forked from YosysHQ/yosys

    SymbiFlow WIP changes for Yosys Open SYnthesis Suite

    C++ 2