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Open source flow for generating bitstreams from Verilog.

Pinned repositories

  1. Random ideas and interesting ideas for things we hope to eventually do.

    48 4

  2. Example designs showing different ways to use SymbiFlow toolchains.

    Verilog 45 15

  3. Documentation for SymbiFlow

    Python 27 9

  4. Forked from YosysHQ/icestorm

    Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

    Python 17 1

  5. Documenting the Xilinx 7-series bit-stream format.

    Python 448 70

  6. Forked from YosysHQ/prjtrellis

    Documenting the Lattice ECP5 bit-stream format.

    Python 7 1


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