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@SymbiFlow

SymbiFlow

Open source flow for generating bitstreams from Verilog.

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  1. sphinxcontrib-hdl-diagrams sphinxcontrib-hdl-diagrams Public

    Sphinx Extension which generates various types of diagrams from Verilog code.

    Python 56 16

  2. vtr-verilog-to-routing vtr-verilog-to-routing Public

    Forked from verilog-to-routing/vtr-verilog-to-routing

    SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++ 37 12

  3. yosys yosys Public

    Forked from YosysHQ/yosys

    SymbiFlow WIP changes for Yosys Open SYnthesis Suite

    C++ 37 9

  4. sphinx-verilog-domain sphinx-verilog-domain Public

    Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

    Python 22 7

  5. nextpnr nextpnr Public

    Forked from YosysHQ/nextpnr

    nextpnr portable FPGA place and route tool

    C++ 20 2

  6. ibex-yosys-build ibex-yosys-build Public

    Testing Ibex build using Yosys and open source toolchains.

    Shell 11 4

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