Merge 32a26e8 into be8d84b

SystemRDL · Mar 20, 2024 · 24091a9 · 24091a9
2 parents be8d84b + 32a26e8
commit 24091a9
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/src/peakrdl_regblock/read_buffering/__init__.py b/src/peakrdl_regblock/read_buffering/__init__.py
@@ -37,8 +37,8 @@ def get_trigger(self, node: RegNode) -> str:
         if isinstance(trigger, RegNode):
             # Trigger is a register.
             # trigger when lowermost address of the register is written
-            regwidth = node.get_property('regwidth')
-            accesswidth = node.get_property('accesswidth')
+            regwidth = trigger.get_property('regwidth')
+            accesswidth = trigger.get_property('accesswidth')
             strb_prefix = self.exp.dereferencer.get_access_strobe(trigger, reduce_substrobes=False)
 
             if accesswidth < regwidth:

diff --git a/src/peakrdl_regblock/write_buffering/__init__.py b/src/peakrdl_regblock/write_buffering/__init__.py
@@ -49,8 +49,8 @@ def get_raw_trigger(self, node: 'RegNode') -> Union[SVInt, str]:
         if isinstance(trigger, RegNode):
             # Trigger is a register.
             # trigger when uppermost address of the register is written
-            regwidth = node.get_property('regwidth')
-            accesswidth = node.get_property('accesswidth')
+            regwidth = trigger.get_property('regwidth')
+            accesswidth = trigger.get_property('accesswidth')
             strb_prefix = self.exp.dereferencer.get_access_strobe(trigger, reduce_substrobes=False)
 
             if accesswidth < regwidth: