Update pylint. UDP unittests

docs/implementation_notes/systemrdl_spec_issues

@@ -119,4 +119,11 @@ Compilation units and their scope not described in SystemRDL spec
         in order to have the least "surprising" effects.
 
         See "multi-file_compilation" notes for more details.
-
+
+--------------------------------------------------------------------------------
+Misc typos in examples
+    15.2.2, Example 1
+        Missing semicolon in some_num_p after "regfile"
+
+    15.2.2, Example 2
+        Enumeration literals are missing their "myEncoding::" prefix

systemrdl/core/properties.py

@@ -98,6 +98,8 @@ def assign_value(self, comp_def, value, src_ref):
         #   - An expression (instance of an Expr subclass)
         if type(value) == bool:
             assign_type = bool
+        elif type(value) == int:
+            assign_type = int
         elif isinstance(value, rdltypes.PrecedenceType):
             assign_type = rdltypes.PrecedenceType
         elif isinstance(value, rdltypes.InterruptType):
@@ -107,6 +109,11 @@ def assign_value(self, comp_def, value, src_ref):
         elif rdltypes.is_user_enum(value):
             assign_type = rdltypes.UserEnum
         else:
+            print(value)
+            self.env.msg.fatal(
+                "LALALA",
+                src_ref
+            )
             raise RuntimeError
 
         # Check if value's type is compatible
@@ -1121,6 +1128,11 @@ def assign_value(self, comp_def, value, src_ref):
         # For user-defined properties, this implies the default value
         # (15.2.2)
         if value is None:
+
+            if self.default is None:
+                # No default was set. Skip assignment entirely
+                return
+
             value = self.default
 
         super().assign_value(comp_def, value, src_ref)

systemrdl/core/validate.py

@@ -93,7 +93,7 @@ def enter_Field(self, node):
         this_f_sw = node.get_property('sw')
 
         # hw property values of w1 or rw1 don't make sense
-        if (this_f_hw == rdltypes.AccessType.w1) or (this_f_hw == rdltypes.AccessType.rw1):
+        if this_f_hw in (rdltypes.AccessType.w1, rdltypes.AccessType.rw1):
             self.msg.error(
                 "Field '%s' hw access property value of %s is meaningless"
                 % (node.inst.inst_name, this_f_hw.name),
@@ -147,11 +147,11 @@ def enter_Field(self, node):
                 prev_f_sw = prev_field.get_property('sw')
 
                 if((prev_f_sw == rdltypes.AccessType.r)
-                    and ((this_f_sw == rdltypes.AccessType.w) or this_f_sw == rdltypes.AccessType.w1)
+                    and (this_f_sw in (rdltypes.AccessType.w, rdltypes.AccessType.w1))
                 ):
                     pass
                 elif((this_f_sw == rdltypes.AccessType.r)
-                    and ((prev_f_sw == rdltypes.AccessType.w) or prev_f_sw == rdltypes.AccessType.w1)
+                    and (prev_f_sw in (rdltypes.AccessType.w, rdltypes.AccessType.w1))
                 ):
                     pass
                 else:

systemrdl/messages.py

@@ -49,6 +49,7 @@ def get_line_text(self):
             for i,line_text in enumerate(fp):
                 if i == self.start_line - 1:
                     return line_text.rstrip("\n")
+        raise RuntimeError
 
     @classmethod
     def from_antlr(cls, antlr_ref):

test/pylint.rc

@@ -123,6 +123,7 @@ disable=
 
         # User ignored
         cyclic-import,
+        useless-return,
         inconsistent-return-statements,
         too-many-locals,
         too-many-branches,

test/rdl_testcases/udp_15.2.2_ex1.rdl

@@ -0,0 +1,19 @@
+property a_map_p { type = string; component = addrmap | regfile; };
+property some_bool_p { type = boolean; component = field; default = false; };
+property some_ref_p { type = ref; component = all; };
+property some_num_p { type = number; default = 0x10; component = field | reg | regfile; };
+
+addrmap foo {
+    reg{
+        field { some_bool_p; } field1;  // Attach some_bool_p to the field
+                                        // with a value of false;
+
+        field { some_bool_p = true; some_num_p; } field2;
+        // Attach some_bool_p to the field with a value of true;
+        field1->some_ref_p = field2; // create a reference
+        some_num_p = 0x20; // Assign this property to the reg and give it value
+    } bar;
+
+    a_map_p; // The property has been bound to the map but it has not been
+            // assigned a value so its value is undefined
+};

test/rdl_testcases/udp_15.2.2_ex2.rdl

@@ -0,0 +1,16 @@
+enum myEncoding {
+    alpha = 1'b0;
+    beta = 1'b1;
+};
+
+property my_enc_prop {
+    type = myEncoding;
+    component = field;
+    default = myEncoding::beta;
+};
+
+addrmap top {
+    reg {
+        field { my_enc_prop = myEncoding::alpha ; } f ;
+    } regA ;
+} ;

test/run.sh

@@ -14,4 +14,4 @@ coverage3 html -d $this_dir/htmlcov
 $this_dir/../examples/print_hierarchy.py $this_dir/../examples/atxmega_spi.rdl > $this_dir/../docs/print_hierarchy_spi.stdout
 
 # Run lint
-pylint3 --rcfile $this_dir/pylint.rc systemrdl | tee $this_dir/lint.rpt
+pylint --rcfile $this_dir/pylint.rc systemrdl | tee $this_dir/lint.rpt

test/test_udp.py

@@ -0,0 +1,43 @@
+
+from .unittest_utils import RDLSourceTestCase
+
+class TestUDP(RDLSourceTestCase):
+
+    def test_15_2_2_ex1(self):
+        root = self.compile(
+            ["rdl_testcases/udp_15.2.2_ex1.rdl"],
+            "foo"
+        )
+
+        foo    = root.find_by_path("foo")
+        bar    = root.find_by_path("foo.bar")
+        field1 = root.find_by_path("foo.bar.field1")
+        field2 = root.find_by_path("foo.bar.field2")
+
+        with self.subTest("foo"):
+            self.assertIs(foo.get_property("some_ref_p"), None)
+            self.assertIs(foo.get_property("a_map_p"), None)
+
+        with self.subTest("bar"):
+            self.assertIs(bar.get_property("some_ref_p"), None)
+            self.assertEqual(bar.get_property("some_num_p"), 0x20)
+
+        with self.subTest("field1"):
+            self.assertEqual(field1.get_property("some_ref_p"), field2)
+            self.assertEqual(field1.get_property("some_bool_p"), False)
+            self.assertIs(field1.get_property("some_num_p"), None)
+
+        with self.subTest("field2"):
+            self.assertIs(field2.get_property("some_ref_p"), None)
+            self.assertEqual(field2.get_property("some_bool_p"), True)
+            self.assertIs(field2.get_property("some_num_p"), 0x10)
+
+    def test_15_2_2_ex2(self):
+        root = self.compile(
+            ["rdl_testcases/udp_15.2.2_ex2.rdl"],
+            "top"
+        )
+
+        f = root.find_by_path("top.regA.f")
+        self.assertEqual(f.get_property("my_enc_prop").value, 0)
+        self.assertEqual(f.get_property("my_enc_prop").name, "alpha")