Non-standard RISC-V Extension

[avianes]

Looking in the instruction decoder I encountered non-standard RISC-V instructions.
https://github.com/T-head-Semi/openc910/blob/a772ed0fe455a7f236ebbdf13c168fd98b467007/C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_id_split_short.v#L355-L631

Opcodes, of these non-standard Store instructions, seem to be decoded here:
https://github.com/T-head-Semi/openc910/blob/a772ed0fe455a7f236ebbdf13c168fd98b467007/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_decd_normal.v#L273-L294
We can clearly see that these are store-type non-standard instructions named: SRB, SRH, SRW, SRD, SURB, SURH, SURW, SURD, SBIB, SBIA, SHIB, SHIA, SWIB, SWIA, SDIA, SDIB, SWD, SDD, FSRW, FSRD, FSURW, FSURD.
Some of these instructions are decoded from the split short decoder I referred to above.

This also applies to load-type instructions. And there is probably some other instructions that I haven't quite identified yet.

I am looking for documentation about this RISC-V extension, but I couldn't find anything.
Could you provide documentation about it?

[CaffreyCC]

You can find these instructions in the user manual under openc910/doc/. The manual is still in Chinese, and the translation of the English version is in progress.

[avianes]

@CaffreyCC thank you very much! As I don't speak Chinese I didn't go deep enough in this document to find the custom ISA Extension.

The pseudo-algorithm description is very useful!

I hope the full Chinese translation will be available soon