[VENTUS][fix] fix add instruction

Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.

Test Plan: fix add instruction

Reviewers: zhoujing

Subscribers: zhoujing

Differential Revision: http://www.tpt.com/D722

Signed-off-by: qinfan <qinfan.wang@terapines.com>

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -1053,6 +1053,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
   setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
+  setOperationAction(ISD::ADD, MVT::i32, Custom);
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
@@ -4008,8 +4009,21 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
 
     return lowerFixedLengthVectorSetccToRVV(Op, DAG);
   }
-  case ISD::ADD:
-    return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL, /*HasMergeOp*/ true);
+  case ISD::ADD: {
+    // If there is any vector type for values.
+    for (const SDValue &V : Op->op_values()) {
+      if (V.getValueType().isVector())
+        return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL, /*HasMergeOp*/ true);
+    }
+
+    SDValue Op1 = Op.getOperand(1);
+
+    if(const auto *Const = dyn_cast<ConstantSDNode>(Op1)) {
+      if(Const->getAPIntValue().isNegative())
+        return lowerToPositiveImm(Op, DAG);
+    }
+    return Op;
+  }
   case ISD::SUB:
     return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL, /*HasMergeOp*/ true);
   case ISD::MUL:
@@ -6716,6 +6730,18 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
   return convertFromScalableVector(VT, Select, DAG, Subtarget);
 }
 
+// If there is a negative imm in add instruction, the instruction will be
+// transformed to sub and the imm will be positive because of the hardware.
+SDValue RISCVTargetLowering::lowerToPositiveImm(SDValue Op, SelectionDAG &DAG) const {
+  signed Imm = Op->getConstantOperandVal(1);
+
+  SDValue NewConst = DAG.getConstant(-Imm, SDLoc(Op->getOperand(1).getNode()), 
+        Op->getOperand(1).getNode()->getValueType(0));
+  SDValue NewValue = DAG.getNode(ISD::SUB, SDLoc(Op), Op->getVTList(),
+        Op->getOperand(0), NewConst);
+  return NewValue;
+}
+
 SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
                                                unsigned NewOpc, bool HasMergeOp,
                                                bool HasMask) const {

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -698,6 +698,7 @@ class RISCVTargetLowering : public TargetLowering {
   SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
                                             SelectionDAG &DAG) const;
+  SDValue lowerToPositiveImm(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
                             bool HasMergeOp = false, bool HasMask = true) const;
   SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,

llvm/test/CodeGen/RISCV/VentusGPGPU/addi.ll

@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=VENTUS %s
+
+; Function Attrs: convergent norecurse nounwind
+define dso_local i32 @sumpi(i32 noundef %a) {
+; VENTUS-LABEL: sumpi:
+; VENTUS:       # %bb.0: # %entry
+; VENTUS-NEXT:    vadd.vi v0, v0, 5
+; VENTUS-NEXT:    ret
+entry:
+  %add = add i32 %a, 5
+  ret i32 %add
+}
+
+; Function Attrs: convergent norecurse nounwind
+define dso_local i32 @sumni(i32 noundef %a) {
+; VENTUS-LABEL: sumni:
+; VENTUS:       # %bb.0: # %entry
+; VENTUS-NEXT:    vsub12.vi v0, v0, 5
+; VENTUS-NEXT:    ret
+entry:
+  %add = add i32 %a, -5
+  ret i32 %add
+}
+