Added the optimized HalfAdder architecture

jtalbert123 · Jul 10, 2017 · a57125a · a57125a
1 parent 19c8318
commit a57125a
Show file tree

Hide file tree

Showing 3 changed files with 48 additions and 11 deletions.
diff --git a/NCL Gates/NCL Gates.cr.mti b/NCL Gates/NCL Gates.cr.mti
@@ -39,6 +39,18 @@ Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr  7
 -- Compiling entity Decoder2_tb
 -- Compiling architecture structural of Decoder2_tb
 
+} {} {}} ncl/impl.vhd {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/impl.vhd}
+Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr  7 2015
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package MATH_REAL
+-- Loading package ncl
+-- Compiling entity THmn
+-- Compiling architecture simple of THmn
+-- Compiling entity THxor0
+-- Compiling architecture behavioral of THxor0
+
 } {} {}} {C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T22_tb.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T22_tb.vhd}
 Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr  7 2015
 -- Loading package STANDARD
@@ -110,14 +122,4 @@ Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr  7
 -- Compiling entity T21_tb
 -- Compiling architecture testbench of T21_tb
 
-} {} {}} {C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/HalfAdder.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/HalfAdder.vhd}
-Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr  7 2015
--- Loading package STANDARD
--- Loading package TEXTIO
--- Loading package std_logic_1164
--- Loading package MATH_REAL
--- Loading package ncl
--- Compiling entity HalfAdder
--- Compiling architecture structural of HalfAdder
-
 } {} {}}
diff --git a/NCL Gates/NCL Gates.mpf b/NCL Gates/NCL Gates.mpf
@@ -2076,7 +2076,7 @@ Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_19 = scripts/tests/t22_tb.tcl
 Project_File_P_19 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
 Project_File_20 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/HalfAdder.vhd
-Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465407 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499644942 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_Sim_Count = 0
 Project_Folder_Count = 5
 Project_Folder_0 = scripts

diff --git a/NCL Gates/ncl/components/HalfAdder.vhd b/NCL Gates/ncl/components/HalfAdder.vhd
@@ -82,3 +82,38 @@ begin
                     output => c0_out);
   c.DATA0 <= c0_out;
 end structural;
+
+architecture optimized of HalfAdder is
+
+begin
+  Sum0: THxor0
+          port map(A => A.DATA0,
+                   B => B.DATA0,
+                   C => A.DATA1,
+                   D => B.DATA1,
+                   output => s.DATA0);
+
+  Sum1: THxor0
+          port map(A => A.DATA1,
+                   B => B.DATA0,
+                   C => A.DATA0,
+                   D => B.DATA1,
+                   output => s.DATA1);
+
+  Carry0: THmn
+          generic map(N => 6, M => 3)
+          port map(inputs(0) => A.DATA0,
+                   inputs(1) => A.DATA0,
+                   inputs(2) => B.DATA0,
+                   inputs(3) => B.DATA0,
+                   inputs(4) => A.DATA1,
+                   inputs(5) => B.DATA1,
+                   output => c.DATA0);
+
+  Carry1: THmn
+          generic map(N => 2, M => 2)
+          port map(inputs(0) => A.DATA1,
+                   inputs(1) => B.DATA1,
+                   output => c.DATA1);
+
+end optimized;