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reworked the optomized FullAdder Implementation
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Talonj123 committed Jul 12, 2017
1 parent a7a9dba commit d645811
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2 changes: 1 addition & 1 deletion NCL Gates/NCL Gates.mpf
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Original file line number Diff line number Diff line change
Expand Up @@ -2058,7 +2058,7 @@ Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
Project_File_10 = scripts/tests/test_threshold_gate.tcl
Project_File_P_10 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
Project_File_11 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/FullAdder.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499740385 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499821360 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_12 = ncl/tests/MUX2_tb.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499382436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_13 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/scripts/tests/HalfAdder.tcl
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182 changes: 104 additions & 78 deletions NCL Gates/ncl/components/FullAdder.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -11,66 +11,11 @@ entity FullAdder is
oC : out ncl_pair);
end FullAdder;

architecture optimized of FullAdder is
signal c0a0b0_ins : std_logic_vector(0 to 2);
signal c0a0b0_out : std_logic;

signal c1a1b1_ins : std_logic_vector(0 to 2);
signal c1a1b1_out : std_logic;

signal oS1_ins : std_logic_vector(0 to 4);
signal oS1_out : std_logic;

signal oS0_ins : std_logic_vector(0 to 4);
signal oS0_out : std_logic;

begin
c0a0b0_ins(0) <= iC.DATA0;
c0a0b0_ins(1) <= a.DATA0;
c0a0b0_ins(2) <= b.DATA0;
T32_C0A0B0 : THmn
generic map(N => 3, M => 2)
port map(inputs => c0a0b0_ins,
output => c0a0b0_out);

c1a1b1_ins(0) <= iC.DATA1;
c1a1b1_ins(1) <= a.DATA1;
c1a1b1_ins(2) <= b.DATA1;
T32_C1A1B1 : THmn
generic map(N => 3, M => 2)
port map(inputs => c1a1b1_ins,
output => c1a1b1_out);

oC.DATA0 <= c0a0b0_out;
oC.DATA1 <= c1a1b1_out;

oS1_ins(0) <= iC.DATA1;
oS1_ins(1) <= a.DATA1;
oS1_ins(2) <= b.DATA1;
oS1_ins(3) <= c0a0b0_out;
oS1_ins(4) <= c0a0b0_out;
T53_oS1 : THmn
generic map(N => 5, M => 3)
port map(inputs => oS1_ins,
output => oS1_out);
oS.DATA1 <= oS1_out;

oS0_ins(0) <= iC.DATA0;
oS0_ins(1) <= a.DATA0;
oS0_ins(2) <= b.DATA0;
oS0_ins(3) <= c1a1b1_out;
oS0_ins(4) <= c1a1b1_out;
T53_oS0 : THmn
generic map(N => 5, M => 3)
port map(inputs => oS0_ins,
output => oS0_out);
oS.DATA0 <= oS0_out;
end optimized;

architecture structural of FullAdder is
type first_layer is array (integer range <>) of std_logic_vector(0 to 2);
signal first_layer_inputs : first_layer(0 to 7);
signal intermediate : std_logic_vector(0 to 7);
signal intermedate : std_logic_vector(0 to 7);
signal inputs : ncl_pair_vector(0 to 2);

begin
Expand All @@ -79,48 +24,129 @@ begin
inputs(0) <= iC;
input_layer: for i in 0 to 7 generate
bits: for ibit in 0 to 2 generate
Input0Selection: if (to_unsigned(2**iBit, 3) and to_unsigned(i, 3)) = 0 generate
first_layer_inputs(i)(iBit) <= inputs(iBit).Data0;
Input0Selection: if (to_unsigned(2**ibit, 3) and to_unsigned(i, 3)) = 0 generate
first_layer_inputs(i)(ibit) <= inputs(ibit).Data0;
end generate;
Input1Selection: if (to_unsigned(2**iBit, 3) and to_unsigned(i, 3)) > 0 generate
first_layer_inputs(i)(iBit) <= inputs(iBit).Data1;
Input1Selection: if (to_unsigned(2**ibit, 3) and to_unsigned(i, 3)) > 0 generate
first_layer_inputs(i)(ibit) <= inputs(ibit).Data1;
end generate;
end generate;
gate: THmn
generic map(M => 3, N => 3)
port map(inputs => first_layer_inputs(i),
output => intermediate(i));
output => intermedate(i));
end generate;

oS0: THmn
generic map(M => 1, N => 4)
port map(inputs(0) => intermediate(0),
inputs(1) => intermediate(3),
inputs(2) => intermediate(5),
inputs(3) => intermediate(6),
port map(inputs(0) => intermedate(0),
inputs(1) => intermedate(3),
inputs(2) => intermedate(5),
inputs(3) => intermedate(6),
output => oS.DATA0);

oS1: THmn
generic map(M => 1, N => 4)
port map(inputs(0) => intermediate(1),
inputs(1) => intermediate(2),
inputs(2) => intermediate(4),
inputs(3) => intermediate(7),
port map(inputs(0) => intermedate(1),
inputs(1) => intermedate(2),
inputs(2) => intermedate(4),
inputs(3) => intermedate(7),
output => oS.DATA1);

oC0: THmn
generic map(M => 1, N => 4)
port map(inputs(0) => intermediate(0),
inputs(1) => intermediate(1),
inputs(2) => intermediate(2),
inputs(3) => intermediate(4),
port map(inputs(0) => intermedate(0),
inputs(1) => intermedate(1),
inputs(2) => intermedate(2),
inputs(3) => intermedate(4),
output => oC.DATA0);

oC1: THmn
generic map(M => 1, N => 4)
port map(inputs(0) => intermediate(3),
inputs(1) => intermediate(5),
inputs(2) => intermediate(6),
inputs(3) => intermediate(7),
port map(inputs(0) => intermedate(3),
inputs(1) => intermedate(5),
inputs(2) => intermedate(6),
inputs(3) => intermedate(7),
output => oC.DATA1);
end structural;
end structural;

architecture optimized of FullAdder is
signal sLT2 : std_logic;
signal sLT3 : std_logic;
signal sGE2 : std_logic;
signal sGE1 : std_logic;
signal sEQ3 : std_logic;
signal sEQ2 : std_logic;
signal sEQ1 : std_logic;
signal sEQ0 : std_logic;

begin
LT2: THmn
generic map(M => 2, N => 3)
port map(inputs(0) => a.DATA0,
inputs(1) => b.DATA0,
inputs(2) => iC.DATA0,
output => sLT2);

GE2: THmn
generic map(M => 2, N => 3)
port map(inputs(0) => a.DATA1,
inputs(1) => b.DATA1,
inputs(2) => iC.DATA1,
output => sGE2);

GE1: THmn
generic map(M => 1, N => 3)
port map(inputs(0) => a.DATA1,
inputs(1) => b.DATA1,
inputs(2) => iC.DATA1,
output => sGE1);

EQ1: THmn
generic map(M => 2, N => 2)
port map(inputs(0) => sGE1,
inputs(1) => sLT2,
output => sEQ1);

EQ3: THmn
generic map(M => 3, N => 3)
port map(inputs(0) => a.DATA1,
inputs(1) => b.DATA1,
inputs(2) => iC.DATA1,
output => sEQ3);

S1: THmn
generic map(M => 1, N => 2)
port map(inputs(0) => sEQ1,
inputs(1) => sEQ3,
output => oS.DATA1);

EQ0: THmn
generic map(M => 3, N => 3)
port map(inputs(0) => a.DATA0,
inputs(1) => b.DATA0,
inputs(2) => iC.DATA0,
output => sEQ0);
LT3: THmn
generic map(M => 1, N => 3)
port map(inputs(0) => a.DATA0,
inputs(1) => b.DATA0,
inputs(2) => iC.DATA0,
output => sLT3);

EQ2: THmn
generic map(M => 2, N => 2)
port map(inputs(0) => sGE2,
inputs(1) => sLT3,
output => sEQ2);

S0: THmn
generic map(M => 1, N => 2)
port map(inputs(0) => sEQ2,
inputs(1) => sEQ0,
output => oS.DATA0);

oC.DATA0 <= sLT2;
oC.DATA1 <= sGE2;

end optimized;

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