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codegen.c
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codegen.c
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/****************************************************************************
*
* Open Watcom Project
*
* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Reserved.
*
* ========================================================================
*
* This file contains Original Code and/or Modifications of Original
* Code as defined in and that are subject to the Sybase Open Watcom
* Public License version 1.0 (the 'License'). You may not use this file
* except in compliance with the License. BY USING THIS FILE YOU AGREE TO
* ALL TERMS AND CONDITIONS OF THE LICENSE. A copy of the License is
* provided with the Original Code and Modifications, and is also
* available at www.sybase.com/developer/opensource.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND SYBASE AND ALL CONTRIBUTORS HEREBY DISCLAIM
* ALL SUCH WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
* NON-INFRINGEMENT. Please see the License for the specific language
* governing rights and limitations under the License.
*
* ========================================================================
*
* Description: instruction encoding, scans opcode table and emits code.
*
****************************************************************************/
#include <limits.h>
#include "globals.h"
#include "memalloc.h"
#include "parser.h"
#include "codegen.h"
#include "fixup.h"
#include "fpfixup.h"
#include "segment.h"
#include "input.h"
#include "listing.h"
#include "reswords.h"
extern const struct opnd_class opnd_clstab[];
#if AVXSUPP
extern struct ReservedWord ResWordTable[];
extern const uint_8 vex_flags[];
#endif
const char szNull[] = {"<NULL>"};
/* v2.03: OutputCodeByte no longer needed */
#define OutputCodeByte( x ) OutputByte( x )
/* segment order must match the one in special.h */
enum prefix_reg {
PREFIX_ES = 0x26,
PREFIX_CS = 0x2E,
PREFIX_SS = 0x36,
PREFIX_DS = 0x3E,
PREFIX_FS = 0x64,
PREFIX_GS = 0x65
};
/* Find size for Compressed byte displacement */
uint_8 GetByteDisp(const struct code_info *CodeInfo)
{
const uint_8 fvarr[2][2][3] = {{{16, 32, 64}, {4, 4, 4}}, // Full Vector (FV)
{{16, 32, 64}, {8, 8, 8}}};
const uint_8 hvarr[2][3] = {{8, 16, 32}, {4, 4, 4}}; // Half Vector (HV)
const uint_8 duparr[3] = {8, 32, 64}; // VMOVDDUP (DUP)
//RXBR00MM
uint_8 n = 0;
bool evexW = (CodeInfo->evex_p1 & EVEX_P1WMASK) >> 7;
enum ttypes tuple = CodeInfo->pinstr->prefix & 0x1F;
bool evexB = (CodeInfo->evex_p2 & EVEX_P2BMASK) >> 4;
uint_8 vctln = (CodeInfo->evex_p2 & EVEX_P2LLMASK) >> 5;
switch(tuple) {
case FV: // Full Vector
n = fvarr[evexW][evexB][vctln];
break;
case HV: // Half Vector
n = hvarr[evexB][vctln];
break;
case FVM: // Full Vector Mem
n = 1 << (vctln + 4);
break;
case T1S8: // Tuple1 Scalar
case T1S16:
n = tuple - T1S8 + 1;
break;
case T1S:
n = evexW ? 8 : 4;
break;
case T1F32: // Tuple1 Fixed
case T1F64:
n = (tuple == T1F32 ? 4 : 8);
break;
case T2: // Tuple2
case T4: // Tuple4
case T8: // Tuple8
if (vctln + 7 <= (evexW + 5) + (tuple - T2 + 1))
n = 0;
else
n = 1 << (tuple - T2 + evexW + 3);
break;
case HVM: // Half Mem
case QVM: // QuarterMem
case OVM: // OctMem
n = 1 << (OVM - tuple + vctln + 1);
break;
case T128: // Mem128
n = 16;
break;
case DUP: // MOVDDUP
n = duparr[vctln];
break;
default:
break;
}
return n;
}
/* Check if compressed displacement is available and stored it in comprdsp */
bool Check4CompDisp8(const struct code_info *CodeInfo, int_8 *comprdsp,int *d, int disp)
{
int_32 disp32 = disp;
uint_8 n;
int_32 disp8;
if (CodeInfo->evex_flag){ //Do it only for EVEX instructions
n = GetByteDisp(CodeInfo);
*d = n;
if (n && !(disp32 & (n - 1))) {
disp8 = disp32 / n;
/* if it fits in Disp8 */
if (disp8 >= -128 && disp8 <= 127) {
*comprdsp = disp8;
return TRUE;
}
}
}
*comprdsp = 0;
return FALSE;
}
static const char sr_prefix[] =
{ PREFIX_ES, PREFIX_CS, PREFIX_SS, PREFIX_DS, PREFIX_FS, PREFIX_GS };
static void output_opc(struct code_info *CodeInfo)
/**************************************************/
/*
* - determine what code should be output and their order.
* - output prefix bytes:
* - LOCK, REPxx,
* - FWAIT (not a prefix, but handled like one)
* - address size prefix 0x67
* - operand size prefix 0x66
* - segment override prefix, branch hints
* - output opcode (1-3), "mod r/m" and "s-i-b" bytes.
*
* Note that jwasm follows Masm strictly here, even if it
* contradicts Intel docs. For example, Masm always emits
* the F2/F3/66 byte before a segment prefix, even if the
* F2/F3/66 byte is a "mantadory prefix".
*/
{
const struct instr_item *ins = CodeInfo->pinstr;
uint_8 tmp;
uint_8 fpfix = FALSE;
int rn;
unsigned char c;
int_8 comprdsp = 0;
DebugMsg1(("output_opc enter, ins.opc/rm=%X/%X, byte1_info=%X CodeInfo->rm=%X opsiz=%u\n", ins->opcode, ins->rm_byte, ins->byte1_info, CodeInfo->rm_byte, CodeInfo->prefix.opsiz));
/*
* Output debug info - line numbers
*/
if (Options.line_numbers)
AddLinnumDataRef(get_curr_srcfile(), GetLineNumber());
/* if it's a FPU instr, reset opsiz */
//if( ins->cpu & P_FPU_MASK ) {
/* v2.02: if it's a FPU or MMX/SSE instr, reset opsiz!
* [this code has been moved here from codegen()]
*/
if (ins->cpu & (P_FPU_MASK | P_MMX | P_SSEALL)) {
#if SSE4SUPP
/* there are 2 exceptions. how to avoid this ugly hack? */
if (CodeInfo->token != T_CRC32 &&
CodeInfo->token != T_POPCNT)
#endif
CodeInfo->prefix.opsiz = FALSE;
}
if ((CodeInfo->token == T_RDRAND) || (CodeInfo->token == T_RDSEED)){
if ((CodeInfo->opnd[OPND1].type == OP_R16) || (CodeInfo->opnd[OPND1].type == OP_AX))
CodeInfo->prefix.opsiz = TRUE;
}
/*
* Check if CPU, FPU and extensions are within the limits
*/
if ((ins->cpu & P_CPU_MASK) > (ModuleInfo.curr_cpu & P_CPU_MASK)
|| (ins->cpu & P_FPU_MASK) > (ModuleInfo.curr_cpu & P_FPU_MASK)
|| (ins->cpu & P_EXT_MASK) > (ModuleInfo.curr_cpu & P_EXT_MASK)) {
DebugMsg(("output_opc: wrong cpu setting: instr.cpu=%X, ModuleInfo.cpu=%X\n",
ins->cpu, ModuleInfo.curr_cpu));
/* if instruction is valid for 16bit cpu, but operands aren't,
then display a more specific error message! */
if (ins->cpu == P_386 &&
((InstrTable[IndexFromToken(CodeInfo->token)].cpu & P_CPU_MASK) <= P_386))
EmitError(INSTRUCTION_FORM_REQUIRES_80386);
else
EmitError(INSTRUCTION_OR_REGISTER_NOT_ACCEPTED_IN_CURRENT_CPU_MODE);
//return( ERROR );
}
//if (CodeInfo->token == T_VMULSS)
// __debugbreak();
/*
* Output FP fixup if required
* the OPs with NOWAIT are the instructions beginning with
* FN, except FNOP.
* the OPs with WAIT are the instructions:
* FCLEX, FDISI, FENI, FINIT, FSAVEx, FSTCW, FSTENVx, FSTSW
*/
if ((ModuleInfo.emulator == TRUE) &&
(CodeInfo->Ofssize == USE16) &&
(ins->cpu & P_FPU_MASK) &&
(ins->allowed_prefix != AP_NO_FWAIT)) {
fpfix = TRUE;
/* v2.04: no error is returned */
AddFloatingPointEmulationFixup(CodeInfo);
}
#if AVXSUPP
/* If VMOVSS or VMOVSD, AVX instructions should have 3 operands if registers used, fix for v2.31 */
if (CodeInfo->token == T_VMOVSS || CodeInfo->token == T_VMOVSD){
if (CodeInfo->reg3 == 0xff){
if (CodeInfo->pinstr->opcode == 0x10 && (CodeInfo->opnd[OPND2].type & OP_M))
;/* that is good, there is no third operand for memory instruction */
else if (CodeInfo->pinstr->opcode == 0x11 && (CodeInfo->opnd[OPND1].type & OP_M) )
;/* that is good, there is no third operand for memory instruction */
else {
EmitErr(INVALID_INSTRUCTION_OPERANDS);
}
}
}
#endif
/*
* Output instruction prefix LOCK, REP or REP[N]E|Z
*/
if (CodeInfo->prefix.ins != EMPTY && (CodeInfo->token < T_VPGATHERDD || CodeInfo->token > T_VGATHERQPS)) {
tmp = InstrTable[IndexFromToken(CodeInfo->prefix.ins)].allowed_prefix;
/* instruction prefix must be ok. However, with -Zm, the plain REP
* is also ok for instructions which expect REPxx.
*/
/* if (ModuleInfo.m510 == TRUE && tmp == AP_REP && ins->allowed_prefix == AP_REPxx) */
/* UASM 2.50 Allow REP in all cases without -Zm */
if (tmp == AP_REP && ins->allowed_prefix == AP_REPxx)
tmp = AP_REPxx;
if (ins->allowed_prefix != tmp) {
EmitError(INSTRUCTION_PREFIX_NOT_ALLOWED);
}
else
OutputCodeByte(InstrTable[IndexFromToken(CodeInfo->prefix.ins)].opcode);
}
/*
* Output FP FWAIT if required
*/
if (ins->cpu & P_FPU_MASK) {
if (CodeInfo->token == T_FWAIT) {
/* v2.04: Masm will always insert a NOP if emulation is active,
* no matter what the current cpu is. The reason is simple: the
* nop is needed because of the fixup which was inserted.
*/
//if(( ModuleInfo.curr_cpu & P_CPU_MASK ) < P_386 ) {
// if(( ModuleInfo.emulator == TRUE ) && ( CodeInfo->Ofssize == USE16 )) {
if (fpfix) {
OutputCodeByte(OP_NOP);
}
}
else if (fpfix || ins->allowed_prefix == AP_FWAIT) {
OutputCodeByte(OP_WAIT);
}
else if (ins->allowed_prefix != AP_NO_FWAIT) {
/* implicit FWAIT synchronization for 8087 (CPU 8086/80186) */
if ((ModuleInfo.curr_cpu & P_CPU_MASK) < P_286)
OutputCodeByte(OP_WAIT);
}
}
/*
* check if address/operand size prefix is to be set
*/
switch (ins->byte1_info) {
case F_16:
if (CodeInfo->Ofssize >= USE32) CodeInfo->prefix.opsiz = TRUE;
break;
case F_32:
if (CodeInfo->Ofssize == USE16) CodeInfo->prefix.opsiz = TRUE;
break;
case F_16A: /* 16-bit JCXZ and LOOPcc */
/* doesnt exist for IA32+ */
if (CodeInfo->Ofssize == USE32) CodeInfo->prefix.adrsiz = TRUE;
break;
case F_32A: /* 32-bit JECXZ and LOOPcc */
#if AMD64_SUPPORT
/* in IA32+, the 32bit version gets an 0x67 prefix */
if (CodeInfo->Ofssize != USE32) CodeInfo->prefix.adrsiz = TRUE;
#else
if( CodeInfo->Ofssize == USE16 ) CodeInfo->prefix.adrsiz = TRUE;
#endif
break;
case F_0FNO66:
CodeInfo->prefix.opsiz = FALSE;
break;
#if AMD64_SUPPORT
case F_48:
case F_480F:
CodeInfo->prefix.rex |= REX_W;
break;
#endif
}
#if AVXSUPP
if ((CodeInfo->token >= T_VSHUFF32X4) && (CodeInfo->token <= T_VSHUFI64X2) &&
((CodeInfo->opnd[OPND1].type & OP_XMM) || (CodeInfo->opnd[OPND2].type & OP_XMM)))
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS); //Only YMM and ZMM alowed
/* John: removed once kn and decorator flag masks were determined not to be required as k0 is implicit */
if ((CodeInfo->token >= T_VBROADCASTF128) && (CodeInfo->token <= T_VPBROADCASTQ)) {
if (decoflags == 0 && CodeInfo->r1type != OP_K)
CodeInfo->evex_flag = 0;
}
/* check if NDS register is present, v2.46.11*/
//if (CodeInfo->evex_flag == FALSE) {
switch (CodeInfo->token){
case T_VADDPD:
case T_VADDSD:
case T_VDIVPD:
case T_VDIVSD:
case T_VMAXPD:
case T_VMAXSD:
case T_VMINPD:
case T_VMINSD:
case T_VMULPD:
case T_VMULSD:
case T_VSQRTSD:
case T_VSUBPD:
case T_VSUBSD:
case T_VADDPS:
case T_VADDSS:
case T_VDIVPS:
case T_VDIVSS:
case T_VMAXPS:
case T_VMAXSS:
case T_VMINPS:
case T_VMINSS:
case T_VMULPS:
case T_VMULSS:
case T_VSQRTSS:
case T_VSUBPS:
case T_VSUBSS:
case T_VCMPPD:
case T_VCMPSD:
case T_VCMPPS:
case T_VCMPSS:
case T_VXORPD:
case T_VORPS:
case T_VXORPS:
/*case T_VPSLLDQ:
case T_VPSRLDQ:
case T_VPSLLW:
case T_VPSLLD:
case T_VPSLLQ:
case T_VPSRAW:
case T_VPSRAD:
case T_VPSRAQ:
case T_VPSRLW:
case T_VPSRLD:
case T_VPSRLQ:*/
if (CodeInfo->r2type == OP_XMM || CodeInfo->r2type == OP_YMM || CodeInfo->r2type == OP_ZMM)
break;
EmitError(INVALID_INSTRUCTION_OPERANDS);
}
//}
/* AVX512 instructions only, the first parameter must be Kn register:
VPCMPB,VPCMPUB,VPCMPD,VPCMPUD,VPCMPQ,VPCMPUQ,VPCMPW,VPCMPUW */
switch (CodeInfo->token){
case T_VPCMPD:
case T_VPCMPUD:
case T_VPCMPQ:
case T_VPCMPUQ:
case T_VPCMPW:
case T_VPCMPUW:
case T_VPCMPB:
case T_VPCMPUB:
if (CodeInfo->r1type == OP_K)
break;
EmitError(INVALID_INSTRUCTION_OPERANDS);
}
/* if (CodeInfo->token >= T_VPORD && CodeInfo->token <= T_PSRLDQ){
if (decoflags == 0 && CodeInfo->r1type != OP_K)
CodeInfo->evex_flag = 0;
}
if (CodeInfo->token == T_VCVTPH2PS || CodeInfo->token == T_VCVTPS2PD ||
CodeInfo->token == T_VRANGEPD ||CodeInfo->token == T_VRANGEPS ||
CodeInfo->token == T_VPTESTNMD ||CodeInfo->token == T_VPTESTNMQ ||
CodeInfo->token == T_VPERM2I128) {
if (decoflags == 0 && CodeInfo->r1type != OP_K)
CodeInfo->evex_flag = 0;
}*/
/* these are only EVEX instructions, v2.46 */
if ((CodeInfo->pinstr->prefix & 0xF00) == IZSZ || (evexflag == TRUE))
CodeInfo->evex_flag = TRUE;
if (!evex){
CodeInfo->evex_flag = FALSE;
if (ResWordTable[CodeInfo->token].flags & RWF_VEX) {
if ((CodeInfo->reg1 > 15 && CodeInfo->reg1 < 32) ||
(CodeInfo->reg2 > 15 && CodeInfo->reg2 < 32) ||
(CodeInfo->reg3 > 15 && CodeInfo->reg3 < 32) ||
CodeInfo->r1type == OP_ZMM || CodeInfo->r2type == OP_ZMM)
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
}
if (CodeInfo->evex_flag == TRUE) {
if (!(vex_flags[CodeInfo->token - VEX_START] & VX_LL))
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
if (CodeInfo->token == T_VCMPSD || CodeInfo->token == T_VCMPSS){
if ( (CodeInfo->r1type > OP_XMM || CodeInfo->r2type > OP_XMM) && CodeInfo->opnd[OPND1].type != OP_K )
EmitError(INVALID_OPERAND_SIZE);
}
if ((CodeInfo->token >= T_VCMPEQSD && CodeInfo->token <= T_VCMPTRUE_USSD)||
(CodeInfo->token >= T_VCMPEQSS && CodeInfo->token <= T_VCMPTRUE_USSS)){
if ((CodeInfo->r1type > OP_XMM || CodeInfo->r2type > OP_XMM) && CodeInfo->opnd[OPND1].type != OP_K )
EmitError(INVALID_OPERAND_SIZE);
}
if (!(ResWordTable[CodeInfo->token].flags & RWF_VEX)) {
#endif
switch (ins->byte1_info) {
case F_660F:
case F_660F38:
case F_660F3A:
CodeInfo->prefix.opsiz = TRUE;
break;
case F_F20F:
case F_F20F38: OutputCodeByte(0xF2); break;
case F_F3: /* PAUSE instruction */
case F_F30F: OutputCodeByte(0xF3); break;
}
#if AVXSUPP
}
#endif
/*
* Output address and operand size prefixes.
* These bytes are NOT compatible with FP emulation fixups,
* which expect that the FWAIT/NOP first "prefix" byte is followed
* by either a segment prefix or the opcode byte.
* Neither Masm nor Uasm emit a warning, though.
*/
if (CodeInfo->prefix.adrsiz == TRUE && (CodeInfo->token < T_VPGATHERDD || CodeInfo->token > T_VSCATTERQPD)&&
CodeInfo->token != T_VCVTPH2PS && CodeInfo->token != T_VCVTPS2PD) {
if (CodeInfo->basereg == 0x10) /* RIP used for relative addressing v2.36 */
;/* don't output 0x67 */
else
OutputCodeByte(ADRSIZ);
#ifdef DEBUG_OUT
if (fpfix)
DebugMsg(("output_opc: ERROR: FP emulation byte sequence destroyed by 32-bit address prefix!\n"));
#endif
}
if (CodeInfo->prefix.opsiz == TRUE) {
#if 1
if ((ModuleInfo.curr_cpu & P_CPU_MASK) < P_386) {
DebugMsg(("output_opc: instruction form requires 386\n"));
EmitError(INSTRUCTION_FORM_REQUIRES_80386);
//return( ERROR ); /* v2.06: don't skip instruction */
}
#endif
if (CodeInfo->token == T_MOVQ && CodeInfo->basereg != 0x10) {
if (CodeInfo->opnd[OPND1].type == OP_XMM && (CodeInfo->opnd[OPND2].type & OP_MS)) {
CodeInfo->prefix.opsiz = FALSE;
OutputCodeByte(0xF3);
}
else if ((CodeInfo->opnd[OPND1].type & OP_MS) && CodeInfo->opnd[OPND2].type == OP_XMM) {
CodeInfo->prefix.opsiz = TRUE;
OutputCodeByte(OPSIZ);
}
else if ((CodeInfo->opnd[OPND1].type == OP_XMM) && (CodeInfo->opnd[OPND2].type & OP_R64)) {
CodeInfo->prefix.opsiz = TRUE;
OutputCodeByte(OPSIZ);
}
else if ((CodeInfo->opnd[OPND2].type == OP_XMM) && (CodeInfo->opnd[OPND1].type & OP_R64)) {
CodeInfo->prefix.opsiz = TRUE;
OutputCodeByte(OPSIZ);
}
}
else
OutputCodeByte(OPSIZ);
}
/*
* Output segment prefix
*/
if (CodeInfo->prefix.RegOverride != EMPTY) {
OutputCodeByte(sr_prefix[CodeInfo->prefix.RegOverride]);
}
if (ins->opnd_dir) {
/* The reg and r/m fields are backwards */
tmp = CodeInfo->rm_byte;
CodeInfo->rm_byte = (tmp & 0xc0) | ((tmp >> 3) & 0x7) | ((tmp << 3) & 0x38);
#if AMD64_SUPPORT
tmp = CodeInfo->prefix.rex;
CodeInfo->prefix.rex = (tmp & 0xFA) | ((tmp & REX_R) >> 2) | ((tmp & REX_B) << 2);
#endif
}
//if (CodeInfo->token == T_VGATHERPF0DPD)
// __debugbreak();
#if AVXSUPP
if (CodeInfo->indextype == OP_XMM || CodeInfo->indextype == OP_YMM || CodeInfo->indextype == OP_ZMM) {
if (CodeInfo->token >= T_VPGATHERDD && CodeInfo->token <= T_VSCATTERQPD)
;
else
EmitErr( AVX_INDEX_REGISTERS_NOT_ALLOWED_HERE );
}
/* ensure missuse of operand types v2.46 */
if (CodeInfo->token >= T_VFMADD132PD && CodeInfo->token <= T_VFNMSUB231SS){
if (CodeInfo->opnd[OPND1].type == CodeInfo->opnd[OPND2].type)
;/* that is OK */
else if (CodeInfo->opnd[OPND2].type & OP_M_ANY)
;/* that is OK */
else
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
/* This is a fix for the memory type and register size v2.46
-----------------------------------------------------------------*/
if ((CodeInfo->token >= T_ADDPD && CodeInfo->token <= T_SUBPS )||
(CodeInfo->token >= T_VADDPD && CodeInfo->token <= T_VSUBPS )){
if (CodeInfo->evex_flag == TRUE) {
if (CodeInfo->opnd[OPND2].type & OP_M_ANY){
CodeInfo->prefix.rex |= EVEX_P0XMASK; /* set X in RXB */
if (CodeInfo->opnd[OPND2].data32l){
CodeInfo->rm_byte &= ~MOD_11; /* clear MOD */
CodeInfo->rm_byte |= MOD_10; /* set disp32 */
}
}
}
if (CodeInfo->opnd[OPND2].type != CodeInfo->opnd[OPND1].type){
if (CodeInfo->opnd[OPND1].type & OP_M_ANY || CodeInfo->opnd[OPND2].type & OP_M_ANY)
;
else
EmitError(INVALID_OPERAND_SIZE);
}
}
/* ---------------------------------------------------------------*/
if (ResWordTable[CodeInfo->token].flags & RWF_VEX) {
uint_8 lbyte = 0;
if (CodeInfo->evex_flag){
lbyte |= 0x4; //bite 3 must be set in P2 WVVVV1PP
}
switch (ins->byte1_info) {
case F_660F:
case F_660F38:
case F_660F3A:
lbyte |= 0x01;
break;
case F_F30F:
case F_F30F38:
lbyte |= 0x02;
break;
case F_F20F:
case F_F20F38:
lbyte |= 0x03;
break;
}
if (CodeInfo->vexregop)
lbyte |= ((16 - CodeInfo->vexregop) << 3);
else {
lbyte |= EVEX_P1VVVV;
CodeInfo->evex_p2 |= EVEX_P2VMASK;
}
/* If there is no decoflags then it is AVX2 instruction with 3 parameters, Uasm 2.15 */
if (CodeInfo->token >= T_VBROADCASTSS && CodeInfo->token <= T_VPBROADCASTMW2D)
{
if (decoflags == 0 && CodeInfo->r1type != OP_K){ /* added code bellow underlined v2.46 */
if ((CodeInfo->reg1 <= 15 && CodeInfo->r1type != OP_ZMM) && ((CodeInfo->pinstr->prefix & 0xF00) != IZSZ))
CodeInfo->evex_flag = 0; /*---------------------------------------*/
else{
CodeInfo->evex_flag = 1;
lbyte |= 4;
}
}
}
if (evexflag == TRUE)
CodeInfo->evex_flag = TRUE;
/* If a Kn mask register not present than it is AVX2 instruction v2.38 */
if (CodeInfo->token >= T_VPGATHERDD && CodeInfo->token <= T_VGATHERQPS)
{
if (decoflags == 0){
if (CodeInfo->reg1 <= 15 && CodeInfo->reg3 <= 15 && CodeInfo->zreg == 0) /* fix for ZMM v2.38 */
CodeInfo->evex_flag = 0;
else EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
/* Check if any pair of the index, mask, or destination registers are not the same,
otherwise this instruction results a GP fault. v2.38 */
if (CodeInfo->reg1 == CodeInfo->reg3 || CodeInfo->reg1 == CodeInfo->indexreg||
CodeInfo->reg3 == CodeInfo->indexreg)
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
}
/* All these instrctions need a Kn mask register present, v2.38 */
if ((CodeInfo->token >= T_VGATHERPF0DPS && CodeInfo->token <= T_VSCATTERQPD)&&(decoflags == 0))
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
/* VCVTTSS2SI can only be used with XMM registers, Uasm 2.16 */
if (CodeInfo->token == T_VCVTTSS2SI || CodeInfo->token == T_VCVTSS2SD){
if (CodeInfo->r2type == OP_YMM || CodeInfo->r2type == OP_ZMM )
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
/* Check size of added missing instructions VRCP28SD, VRCP28SS, VRCP28PD, VRCP28PS
VRSQRT28PD, VRSQRT28PS, VRSQRT28SD, VRSQRT28SS, VEXP2PD, VEXP2PS Uasm 2.16 */
switch (CodeInfo->token){
case T_VRCP28SD:
case T_VRSQRT28SD:
if (CodeInfo->mem_type != MT_EMPTY && CodeInfo->mem_type != MT_QWORD )
goto error;
if ((CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM) &&
CodeInfo->opnd[OPND1].type == OP_XMM || CodeInfo->opnd[OPND1].type == OP_M)
break;
else goto error;
case T_VRCP28SS:
case T_VRSQRT28SS:
if (CodeInfo->mem_type != MT_EMPTY && CodeInfo->mem_type != MT_DWORD )
goto error;
if ((CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM) &&
CodeInfo->opnd[OPND1].type == OP_XMM || CodeInfo->opnd[OPND1].type == OP_M)
break;
case T_VPCLMULQDQ:
case T_VAESDECLAST:
case T_VAESENCLAST:
case T_VAESDEC:
case T_VAESENC:
if (CodeInfo->mem_type != MT_EMPTY && CodeInfo->mem_type != MT_OWORD )
goto error;
if ((CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM) &&
CodeInfo->opnd[OPND1].type == OP_XMM || CodeInfo->opnd[OPND1].type == OP_M)
break;
else goto error;
case T_VAESKEYGENASSIST:
if (CodeInfo->mem_type != MT_EMPTY && CodeInfo->mem_type != MT_OWORD )
goto error;
if ((CodeInfo->r1type == OP_XMM) &&
CodeInfo->opnd[OPND2].type == OP_XMM || CodeInfo->opnd[OPND2].type == OP_M128 ||
CodeInfo->opnd[OPND2].type == OP_M)
break;
else goto error;
case T_VRCP28PD:
case T_VRCP28PS:
case T_VRSQRT28PD:
case T_VRSQRT28PS:
case T_VEXP2PD:
case T_VEXP2PS:
if ((CodeInfo->r1type == OP_ZMM) && (CodeInfo->opnd[OPND2].type == OP_ZMM ||
CodeInfo->opnd[OPND2].type & OP_M_ANY )) /* changed to '& OP_M_ANY' v2.46 */
break;
else goto error;
}
switch (CodeInfo->token){
case T_VCVTSS2USI:
case T_VCVTSS2SI :
case T_VCVTSS2SD :
case T_VCVTSI2SS :
case T_VCVTSI2SD :
case T_VCVTSD2SS :
case T_VCVTSD2USI:
case T_VCVTSD2SI :
if (CodeInfo->r1type == OP_YMM || CodeInfo->opnd[OPND2].type == OP_YMM)
goto error;
}
/* Validate use of proper GPR size for VPINSRB, VPINSRW, VPINSRD, VPINSRQ, VPEXTRB, VPEXTRW, VPEXTRD, VPEXTRQ, Uasm 2.16
* MT_EMPTY is OK because instructions mnemonics are teling the size
*/
switch (CodeInfo->token){
case T_VPINSRB:
if ((CodeInfo->opnd[OPND2].type == OP_R32 || CodeInfo->mem_type == MT_BYTE || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM))
;// That is correct
else goto error;
break;
case T_VPINSRW:
if ((CodeInfo->opnd[OPND2].type == OP_R32 || CodeInfo->mem_type == MT_WORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM))
;// That is correct
else goto error;
break;
case T_VPINSRD:
if ((CodeInfo->opnd[OPND2].type == OP_R32 || CodeInfo->mem_type == MT_DWORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM))
;// That is correct
else goto error;
break;
case T_VPINSRQ: // only VPINSRQ can have OP_R64 or MT_QWORD
if ((CodeInfo->opnd[OPND2].type == OP_R64 || CodeInfo->mem_type == MT_QWORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r1type == OP_XMM && CodeInfo->r2type == OP_XMM))
;// That is correct
else goto error;
break;
case T_VPEXTRB:
if ((CodeInfo->opnd[OPND1].type == OP_R32 || CodeInfo->mem_type == MT_BYTE || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r2type == OP_XMM ))
;//That is correct
else goto error;
break;
case T_VPEXTRW:
if ((CodeInfo->opnd[OPND1].type == OP_R32 || CodeInfo->mem_type == MT_WORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r2type == OP_XMM ))
;//That is correct
else goto error;
break;
case T_VPEXTRD:
if ((CodeInfo->opnd[OPND1].type == OP_R32 || CodeInfo->mem_type == MT_DWORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r2type == OP_XMM ))
;//That is correct
else goto error;
break;
case T_VPEXTRQ:
if ((CodeInfo->opnd[OPND1].type == OP_R64 || CodeInfo->mem_type == MT_QWORD || CodeInfo->mem_type == MT_EMPTY) &&
(CodeInfo->r2type == OP_XMM ))
;//That is correct
else goto error;
break;
error:
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
/* emit 4 byte (0x62), 3 (0xC4) or 2 (0xC5) byte VEX prefix */
if ((CodeInfo->token == T_VMOVMSKPD )||(CodeInfo->token == T_VMOVMSKPS ))
CodeInfo->prefix.rex &= ~REX_W;
//if (CodeInfo->indexreg == EMPTY) tmp = 0xB4;
if (( ins->byte1_info >= F_0F38) || ( CodeInfo->prefix.rex & ( REX_B | REX_X | REX_W ) )||
(( ins->byte1_info == F_0F) && (CodeInfo->token == T_KMOVQ )) || (ins->byte1_info == F_660F) &&
(CodeInfo->token == T_KMOVD )){
uint_8 byte1 = 0; //RXBR00MM
/* first byte is 0xC4 in 3 byte VEX prefix */
if (CodeInfo->evex_flag)
OutputCodeByte( 0x62 ); //AVX512 EVEX first byte
else{
/* These instructions if, not 0x62, can be only 0xC5, Uasm 2.16 */
if (CodeInfo->token == T_VPMOVMSKB){
if(ins->byte1_info == F_0F && (CodeInfo->prefix.rex & REX_B == 0)&&
(CodeInfo->prefix.rex & REX_X == 0) && (CodeInfo->prefix.rex & REX_W == 8))
goto outC5; // go handle 0xC5 instruction
//CodeInfo->prefix.rex &= ~REX_W; // clear the W bit.
if(CodeInfo->reg3 > 7) lbyte |= 1;
}
if ((CodeInfo->token >= T_VPSLLDQ && CodeInfo->token <= T_VPSRLQ)||
(CodeInfo->token == T_VXORPD || CodeInfo->token ==T_VXORPS)){
/* first and second operand can not be memory, v2.46.11 */
if (CodeInfo->r1type < OP_XMM || CodeInfo->r2type < OP_XMM)
EmitError(INVALID_INSTRUCTION_OPERANDS);
if ((CodeInfo->reg2 <= 7)&&(CodeInfo->reg3 <= 7) && ((CodeInfo->opnd[OPND2].type & OP_M_ANY ) == 0))
goto outC5; // go handle 0xC5 instruction
/* John: Validate 3 operand vex form */
if (CodeInfo->opnd[OPND3].type == OP_NONE && CodeInfo->vexregop == 0 &&
(vex_flags[CodeInfo->token - VEX_START] & VX_NND) == 0 &&
(vex_flags[CodeInfo->token - VEX_START] & VX_NMEM) == 0)
{
EmitError(INVALID_INSTRUCTION_OPERANDS);
}
OutputCodeByte(0xC4);
CodeInfo->first_byte = 0xC4;
}
else
{
/* John: Validate 3 operand vex form */
if (CodeInfo->opnd[OPND3].type == OP_NONE && CodeInfo->vexregop == 0 &&
(vex_flags[CodeInfo->token - VEX_START] & VX_NND)==0 &&
(vex_flags[CodeInfo->token - VEX_START] & VX_NMEM)==0)
{
EmitError(INVALID_INSTRUCTION_OPERANDS);
}
OutputCodeByte(0xC4);
CodeInfo->first_byte = 0xC4;
}
if (CodeInfo->opnd[OPND1].type == OP_YMM || CodeInfo->opnd[OPND2].type == OP_YMM)
lbyte |= 0x04;
else
lbyte &= ~0x04;
CodeInfo->tuple = 0;
/* This fixes AVX REX_W wide 32 <-> 64 instructions third byte bit W || (CodeInfo->token == T_VMOVQ) */
if ((CodeInfo->token >= T_VADDPD && CodeInfo->token <= T_VMOVAPS) ||
(CodeInfo->token == T_VMOVD) ||(CodeInfo->token == T_VPANDN)||
(CodeInfo->token == T_VMOVSD)|| (CodeInfo->token == T_VMOVSS)||(CodeInfo->token == T_VPAND))
lbyte &= ~EVEX_P1WMASK; //make sure it is not set if WIG
else
lbyte |= ((CodeInfo->pinstr->prefix) >> 8 & 0x80); // set only W bit if 64 bit
}
switch ( ins->byte1_info ) {
case F_0F38:
case F_660F38:
case F_F20F38:
case F_F30F38:
byte1 |= 0x02;
break;
case F_0F3A:
case F_660F3A:
case F_F20F3A:
byte1 |= 0x03;
break;
default:
if ( ins->byte1_info >= F_0F )
byte1 |= 0x01;
}
byte1 |= ((CodeInfo->prefix.rex & REX_B) ? 0 : 0x20);/* REX_B regno 0-7 <-> 8-15 of ModR/M or SIB base */
byte1 |= ((CodeInfo->prefix.rex & REX_X) ? 0 : 0x40);/* REX_X regno 0-7 <-> 8-15 of SIB index */
byte1 |= ((CodeInfo->prefix.rex & REX_R) ? 0 : 0x80);/* REX_R regno 0-7 <-> 8-15 of ModR/M REG */
/* check that second operand is not memory operand, v2.46 */
if (CodeInfo->opnd[OPND2].type & OP_M_ANY)
;/* skip */
else if (CodeInfo->evex_flag && CodeInfo->reg2 <= 15)
byte1 |= EVEX_P0R1MASK;
/* second byte is RXBm mmmm of 3 byte VEX prefix */ /* REX_W wide 32 <-> 64 */
if (CodeInfo->evex_flag) {
if (CodeInfo->token == T_VEXTRACTPS)
;/* skip */
else{
if ((CodeInfo->opnd[OPND1].type & OP_M_ANY) || (CodeInfo->opnd[OPND2].type & OP_M_ANY) ||
(CodeInfo->opnd[OPND3].type & OP_M_ANY)) CodeInfo->tuple = TRUE;
lbyte &= ~EVEX_P1WMASK;
lbyte |= ((CodeInfo->pinstr->prefix) >> 8 & 0x80);
if ((CodeInfo->opnd[OPND2].type == OP_M64) || (CodeInfo->opnd[OPND1].type == OP_M64))
lbyte |= EVEX_P1WMASK;
if ((CodeInfo->opnd[OPND2].type == OP_R32) || (CodeInfo->opnd[OPND2].type == OP_EAX) ||
(CodeInfo->opnd[OPND1].type == OP_R32) || (CodeInfo->opnd[OPND1].type == OP_EAX)){
lbyte &= ~EVEX_P1WMASK;
}
if (((CodeInfo->opnd[OPND1].type & OP_M_ANY) == 0) && CodeInfo->token != T_VPEXTRD &&
(CodeInfo->token != T_VCVTPS2PD) && CodeInfo->token != T_VPEXTRB &&
(CodeInfo->token != T_VCVTPS2PH) && CodeInfo->token != T_VPEXTRW &&
CodeInfo->token != T_VPEXTRQ) { //CodeInfo->token != T_VPMOVQB &&
if (CodeInfo->reg1 <= 15)
byte1 |= EVEX_P0R1MASK;
else
byte1 &= ~EVEX_P0R1MASK;
if ((CodeInfo->reg1 <= 7) || (CodeInfo->reg1 >= 16 && CodeInfo->reg1 <= 23))
byte1 |= EVEX_P0RMASK;
else
byte1 &= ~EVEX_P0RMASK;
if (CodeInfo->reg3 != 0xff) {
rn = CodeInfo->reg3;
}
else if (CodeInfo->basereg != 0xff)
rn = CodeInfo->basereg;
else rn = CodeInfo->reg2;
if (rn > 15){
rn -= 15;
byte1 &= ~EVEX_P0XMASK;
}
/* if third register is a mask register and not memory opperand than don't touch EVEX_P0BMASK v2.38 */
if (CodeInfo->reg3 != 0xff && CodeInfo->basereg == 0xff);
else if (rn <= 7)byte1 |= EVEX_P0BMASK;
else byte1 &= ~EVEX_P0BMASK;
}
}
}
if (CodeInfo->token >= T_VPSCATTERDD && CodeInfo->token <= T_VSCATTERQPD){
if (CodeInfo->reg2 <= 15) byte1 |= EVEX_P0R1MASK;
else byte1 &= ~EVEX_P0R1MASK;
if (CodeInfo->reg2 <= 7 ) byte1 |= EVEX_P0RMASK;
else if (CodeInfo->reg2 >= 16 && CodeInfo->reg2 <= 23) byte1 |= EVEX_P0RMASK;
else byte1 &= ~EVEX_P0RMASK;
}
if (((CodeInfo->token == T_VMOVHPS)||(CodeInfo->token == T_VMOVLPS)) && (CodeInfo->opnd[OPND2].type & OP_XMM)){
if ((CodeInfo->reg2 > 7))
byte1 &= ~EVEX_P0RMASK;
lbyte &= ~EVEX_P1WMASK;
}
if ((CodeInfo->token == T_VMOVNTPD)||(CodeInfo->token == T_VMOVNTPS)||
(CodeInfo->token >= T_VPMOVQB)&&(CodeInfo->token <= T_VPMOVUSWB)){
if (CodeInfo->reg2 <= 15) byte1 |= EVEX_P0R1MASK;
else byte1 &= ~EVEX_P0R1MASK;
if ((CodeInfo->reg2 <= 7) || (CodeInfo->reg2 >= 16 && CodeInfo->reg2 <= 23))
byte1 |= EVEX_P0RMASK;
else byte1 &= ~EVEX_P0RMASK;
if (CodeInfo->opnd[OPND1].type & OP_M_ANY == 0){
if (CodeInfo->reg1 <= 15) byte1 |= EVEX_P0XMASK;
else byte1 &= ~EVEX_P0XMASK;
if ((CodeInfo->reg1 <= 7) || (CodeInfo->reg1 >= 16 && CodeInfo->reg1 <= 23))
byte1 |= EVEX_P0BMASK;
else byte1 &= ~EVEX_P0BMASK;
}
}
if (CodeInfo->opnd[OPND2].type & OP_I8_U){
if ((CodeInfo->token >= T_VPSLLW) && (CodeInfo->token <= T_VPSRLQ) ||
(CodeInfo->token >= T_VPSLLVD) && (CodeInfo->token <= T_VPSRLVW)){
byte1 |= EVEX_P0R1MASK;
byte1 |= EVEX_P0RMASK;
if ((CodeInfo->opnd[OPND1].type == OP_R64) || (CodeInfo->opnd[OPND1].type == OP_RAX) ||
(CodeInfo->opnd[OPND1].type == OP_R32) || (CodeInfo->opnd[OPND1].type == OP_EAX)){
if (CodeInfo->basereg != 0xFF){
if (CodeInfo->basereg <= 7)
byte1 |= EVEX_P0BMASK;
else
byte1 &= ~EVEX_P0BMASK;
}
if (CodeInfo->indexreg != 0xFF){
if (CodeInfo->indexreg <= 7)
byte1 |= EVEX_P0XMASK;
else
byte1 &= ~EVEX_P0XMASK;
}
}
else if (!CodeInfo->evex_flag)
byte1 &= ~EVEX_P0R1MASK;
}
}
if ((CodeInfo->token == T_VRNDSCALEPD) || (CodeInfo->token == T_VRNDSCALEPS)){
if (((CodeInfo->r2type &= OP_R64)||(CodeInfo->r2type &= OP_R32))&&
(CodeInfo->vexconst)) {
if (CodeInfo->indexreg != 0xff){
if (CodeInfo->reg1 <= 7)
byte1 |= EVEX_P0XMASK;
else
byte1 &= ~EVEX_P0XMASK;
}
}
}
if (((CodeInfo->token == T_VEXTRACTF32x8)||(CodeInfo->token == T_VEXTRACTF64x4))
&& !(CodeInfo->opnd[OPND1].type & OP_M_ANY)) {
if (CodeInfo->reg2 <= 15) byte1 |= EVEX_P0R1MASK;
else byte1 &= ~EVEX_P0R1MASK;
if ((CodeInfo->reg2 <= 7) || (CodeInfo->reg2 >= 16 && CodeInfo->reg2 <= 23))
byte1 |= EVEX_P0RMASK;
else
byte1 &= ~EVEX_P0RMASK;
if (CodeInfo->reg1 <= 15) byte1 |= EVEX_P0XMASK;
else byte1 &= ~EVEX_P0XMASK;
}
if (((CodeInfo->token >= T_BEXTR)&&(CodeInfo->token <= T_SHRX)||(CodeInfo->token == T_BZHI)&&
(CodeInfo->indexreg != 0xFF))){
byte1 &= 0xE3;
if (CodeInfo->indexreg > 7 && CodeInfo->indexreg <= 31)
byte1 &= ~0x10;
}
if (CodeInfo->token == T_VCVTPH2PS || CodeInfo->token == T_VCVTPD2UDQ || CodeInfo->token == T_VCVTQQ2PD||
CodeInfo->token == T_VCVTPD2DQ || CodeInfo->token == T_VCVTDQ2PD){
if ((CodeInfo->reg1 <= 7) || (CodeInfo->reg1 >= 16 && CodeInfo->reg1 <= 23))
byte1 |= EVEX_P0RMASK;
else
byte1 &= ~EVEX_P0RMASK;
if (CodeInfo->indexreg != 0xff){
if (CodeInfo->indexreg <= 7) byte1 |= EVEX_P0XMASK;
else byte1 &= ~EVEX_P0XMASK;
}
if (CodeInfo->token == T_VCVTDQ2PD || CodeInfo->token == T_VCVTPS2PD)
CodeInfo->evex_p2 &= ~EVEX_P2L1MASK;
}
if (CodeInfo->token == T_VPCMPEQQ || CodeInfo->token == T_VPCMPEQD ||
CodeInfo->token == T_VPCMPEQW || CodeInfo->token == T_VPCMPEQB){
if (CodeInfo->r1type == OP_ZMM)
EmitError(INVALID_COMBINATION_OF_OPCODE_AND_OPERANDS);
}
/* fix for P0 output v2.46 if (CodeInfo->opnd[OPND1].type == OP_XMM && CodeInfo->opnd[OPND2].type == OP_XMM) ins->opcode = 0x7E;*/
if (CodeInfo->token == T_VMOVQ){
if (CodeInfo->opnd[OPND1].type & OP_R64){
if (CodeInfo->evex_flag){
if (CodeInfo->reg2 <= 15) byte1 |= EVEX_P0R1MASK;
else byte1 &= ~EVEX_P0R1MASK;
}
if ((CodeInfo->reg2 <= 7) || (CodeInfo->reg2 >= 16 && CodeInfo->reg2 <= 23))
byte1 |= EVEX_P0RMASK;
else byte1 &= ~EVEX_P0RMASK;
byte1 |= EVEX_P0XMASK;
}
else if (CodeInfo->opnd[OPND1].type & OP_M64){
if (CodeInfo->evex_flag){
if (CodeInfo->reg2 <= 15) byte1 |= EVEX_P0R1MASK;
else byte1 &= ~EVEX_P0R1MASK;
}
if ((CodeInfo->reg2 <= 7) || (CodeInfo->reg2 >= 16 && CodeInfo->reg2 <= 23))
byte1 |= EVEX_P0RMASK;
else byte1 &= ~EVEX_P0RMASK;
}
}
/* fix v2.46 */
if (CodeInfo->token == T_VCVTPS2PD || CodeInfo->token == T_VCVTPH2PS ||
CodeInfo->token == T_VCVTPS2PH | CodeInfo->token == T_VCVTQQ2PD){
/* don't check for memory to reg here */