[WARNING ORD-2013] instance dcache/data/array_0_0_0_ext LEF master array_256x64 not found.

[oharboe]

What is OpenROAD telling me here?

[maliberty]

You have an instance of array_256x64 in your Verilog but you haven't loaded a LEF for that into OR.

[oharboe]

I get this message in floorplan.tcl

It should be legal to specify the Verilog in synthesis, even if I have a corresponding .lef file, i.e. the Verilog is superfluous in syntheis, right?

I get this error message in floorplan.tcl and there is no array_256x64 in 1_synth.v

[maliberty]

I can't understand your comment. Its is a warning and doesn't relate to synthesis per-se. OR is just telling you that you will have no physical implementation of this block and that will make your results dubious.

[oharboe]

I will create a testcase.