Cleaner MMAP-ing and clock logic.

altera_ram.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_ram.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_ram.cmp"]

altera_ram.vhd

@@ -0,0 +1,193 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_ram.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_ram IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		byteena		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '1');
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		inclock		: IN STD_LOGIC  := '1';
+		outclock		: IN STD_LOGIC ;
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END altera_ram;
+
+
+ARCHITECTURE SYN OF altera_ram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		byte_size		: NATURAL;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			byteena_a	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		byte_size => 8,
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		width_a => 32,
+		width_byteena_a => 4
+	)
+	PORT MAP (
+		wren_a => wren,
+		clock0 => inclock,
+		clock1 => outclock,
+		byteena_a => byteena,
+		address_a => address,
+		data_a => data,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
+-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
+-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC byteena[3..0]
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC inclock
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

clock_1hz.vhd

@@ -4,35 +4,36 @@ use ieee.std_logic_1164.all;
 
 entity clock_1hz is
    port (
-           clk : in std_logic;
-           clk_out : out std_logic;
-           clk_out_ram : out std_logic
+           clk : in std_logic;
+           reset : in std_logic;
+
+           insmem_clk : out std_logic_vector(2 downto 0);
+           ram_clk : out std_logic_vector(2 downto 0);
+           cpu_clk : out std_logic
         );
 end;
 
 architecture synth of clock_1hz is
 
-   signal count : std_logic_vector(31 downto 0);
-   signal clk_cnt : std_logic_vector(1 downto 0);
+   signal count : integer := 0;
+   signal clk_cnt : std_logic_vector(6 downto 0) := "0000001";
 
 begin
-   process (clk) begin
-      if rising_edge(clk) then
-
-
-         if (count = x"00000100") then
-            if (clk_cnt = "11") then
-				clk_cnt <= "00";
-			else
-				clk_cnt <= clk_cnt + '1';
-			end if;
-            count <= x"00000000";
+   process (clk, reset) begin
+      if (reset = '1') then
+		  count <= 0;
+		  clk_cnt <= "0000001";
+      elsif rising_edge(clk) then 
+         if (count = 10) then
+            clk_cnt <= clk_cnt(5 downto 0) & clk_cnt(6); -- rotate the clk bits
+            count <= 0;
          else
-            count <= count + '1';
+            count <= count + 1;
 
          end if;
       end if;
    end process;
-   clk_out <= clk_cnt(1);
-   clk_out_ram <= clk_cnt(0);
+   insmem_clk <= clk_cnt(2 downto 0);
+   ram_clk <= clk_cnt(5 downto 3);
+   cpu_clk <= clk_cnt(6);
 end;