Add OHO GODIL support

zpu/hdl/zpuino/boards/oho_godil/Makefile

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+PROJECT=oho_godil
+PART=xc3s500e-vq100-4
+
+# For bootloader
+BOARD=OHO_GODIL
+SIZE=32768
+DEFINES="-D__S3E_500__ -DBOARD_ID=0xA5010F00 -DBOARD_MEMORYSIZE=0x8000"
+
+all: ${PROJECT}_routed.bit ${PROJECT}_routed.bin
+
+prom-generic-dp-32.vhd:
+	$(MAKE) -C ../../bootloader BOARD=$(BOARD) SIZE=$(SIZE) DEFINES=$(DEFINES)
+	cp ../../bootloader/prom-generic-dp-32.vhd .
+
+${PROJECT}.ngc: prom-generic-dp-32.vhd
+	mkdir -p xst/projnav.tmp/
+	xst -intstyle ise -ifn ${PROJECT}.xst -ofn ${PROJECT}.syr
+
+${PROJECT}.ngd: ${PROJECT}.ngc
+	ngdbuild -intstyle ise -dd _ngo -nt timestamp \
+	-uc ${PROJECT}.ucf -p ${PART} ${PROJECT}.ngc ${PROJECT}.ngd
+
+${PROJECT}.ncd: ${PROJECT}.ngd
+	map -intstyle ise -p ${PART} \
+	-cm speed -detail -ir off -ignore_keep_hierarchy -pr b -timing -ol high -logic_opt on  \
+	-o ${PROJECT}.ncd ${PROJECT}.ngd ${PROJECT}.pcf 
+
+${PROJECT}_routed.ncd: ${PROJECT}.ncd
+	par -w -intstyle ise -ol high -t 1 ${PROJECT}.ncd ${PROJECT}_routed.ncd ${PROJECT}.pcf
+
+${PROJECT}_routed.bit: ${PROJECT}_routed.ncd
+	bitgen -f ${PROJECT}.ut ${PROJECT}_routed.ncd
+
+${PROJECT}_routed.bin: ${PROJECT}_routed.bit
+	promgen -w -spi -p bin -o ${PROJECT}_routed.bin -s 1024 -u 0 ${PROJECT}_routed.bit
+
+clean:
+	@rm -rf ${PROJECT}.{ngc,ngd,ncd,_routed.ncd,pcf,bit,_routed.bit} prom-generic-dp-32.vhd
+	$(MAKE) -C ../../bootloader clean

zpu/hdl/zpuino/boards/oho_godil/clkgen.vhd

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+--
+--  System Clock generator for ZPUINO (Nexys2 board)
+-- 
+--  Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
+-- 
+--  Version: 1.0
+-- 
+--  The FreeBSD license
+--  
+--  Redistribution and use in source and binary forms, with or without
+--  modification, are permitted provided that the following conditions
+--  are met:
+--  
+--  1. Redistributions of source code must retain the above copyright
+--     notice, this list of conditions and the following disclaimer.
+--  2. Redistributions in binary form must reproduce the above
+--     copyright notice, this list of conditions and the following
+--     disclaimer in the documentation and/or other materials
+--     provided with the distribution.
+--  
+--  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+--  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+--  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+--  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+--  ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+--  INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+--  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+--  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+--  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+--  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+--  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+--  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--  
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all; 
+use IEEE.std_logic_unsigned.all; 
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+entity clkgen is
+  port (
+    clkin:  in std_logic;
+    rstin:  in std_logic;
+    clkout: out std_logic;
+    rstout: out std_logic
+  );
+end entity clkgen;
+
+architecture behave of clkgen is
+
+signal dcmlocked_a: std_logic;
+signal dcmlocked_b: std_logic;
+signal dcmclock: std_logic;
+signal dcmclock_b: std_logic;
+
+signal rst1_q: std_logic;
+signal rst2_q: std_logic;
+signal clkout_i: std_logic;
+signal clkout_tmp: std_logic;
+signal clkin_i: std_logic;
+signal clkfb: std_logic;
+signal clkfb_b: std_logic;
+signal clk0: std_logic;
+signal clk0_b: std_logic;
+begin
+
+  clkout <= clkout_i;
+
+  rstout <= rst1_q;
+
+  process(dcmlocked_a,dcmlocked_b, clkout_i, rstin)
+  begin
+    if dcmlocked_a='0' or dcmlocked_b='0' or rstin='1' then
+      rst1_q <= '1';
+      rst2_q <= '1';
+    else
+      if rising_edge(clkout_i) then
+        rst1_q <= rst2_q;
+        rst2_q <= '0';
+      end if;
+    end if;
+  end process;
+
+  -- Clock buffers
+
+--  clkfx_inst: BUFG
+--    port map (
+--      I =>  dcmclock,
+--      O =>  clkout_tmp
+--    );
+  clkout_tmp <= dcmclock;
+
+  clkfx2_inst: BUFG
+    port map (
+      I =>  dcmclock_b,
+      O =>  clkout_i
+    );
+
+  clkin_inst: IBUFG
+    port map (
+      I =>  clkin,
+      O =>  clkin_i
+    );
+
+  clkfb_inst: BUFG
+    port map (
+      I=> clk0,
+      O=> clkfb
+    );
+
+  clkfb2_inst: BUFG
+    port map (
+      I=> clk0_b,
+      O=> clkfb_b
+    );
+
+
+DCM_inst : DCM -- Generate a 32MHz clock
+  generic map (
+    CLKDV_DIVIDE => 2.0,          -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+    CLKFX_DIVIDE => 20,--8,            -- Can be any integer from 1 to 32
+    CLKFX_MULTIPLY => 13,--23,          -- Can be any integer from 1 to 32
+    CLKIN_DIVIDE_BY_2 => FALSE,   -- TRUE/FALSE to enable CLKIN divide by two feature
+    CLKIN_PERIOD => 20.00,         -- Specify period of input clock
+    CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+    CLK_FEEDBACK => "1X",       -- Specify clock feedback of NONE, 1X or 2X
+    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+    DFS_FREQUENCY_MODE => "LOW",            -- HIGH or LOW frequency mode for frequency synthesis
+    DLL_FREQUENCY_MODE => "LOW",            -- HIGH or LOW frequency mode for DLL
+    DUTY_CYCLE_CORRECTION => TRUE,          -- Duty cycle correction, TRUE or FALSE
+    FACTORY_JF => X"C080",                  -- FACTORY JF Values
+    PHASE_SHIFT => 0,                       -- Amount of fixed phase shift from -255 to 255
+    STARTUP_WAIT => FALSE                   -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+    ) 
+  port map (
+    CLK0 => clk0, -- 0 degree DCM CLK ouptput
+    CLK180 => open, -- 180 degree DCM CLK output
+    CLK270 => open, -- 270 degree DCM CLK output
+    CLK2X => open, -- 2X DCM CLK output
+    CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+    CLK90 => open, -- 90 degree DCM CLK output
+    CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+    CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
+    CLKFX180 => open, -- 180 degree CLK synthesis out
+    LOCKED => dcmlocked_a, -- DCM LOCK status output
+    PSDONE => open, -- Dynamic phase adjust done output
+    STATUS => open, -- 8-bit DCM status bits output
+    CLKFB => clkfb, -- DCM clock feedback
+    CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
+    PSCLK => '0', -- Dynamic phase adjust clock input
+    PSEN => '0', -- Dynamic phase adjust enable input
+    PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
+    RST => '0' -- DCM asynchronous reset input
+  );
+
+
+DCM2_inst : DCM -- Generate 96Mhz
+  generic map (
+    CLKDV_DIVIDE => 2.0,          -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+    CLKFX_DIVIDE => 1,--8,            -- Can be any integer from 1 to 32
+    CLKFX_MULTIPLY => 3,--23,          -- Can be any integer from 1 to 32
+    CLKIN_DIVIDE_BY_2 => FALSE,   -- TRUE/FALSE to enable CLKIN divide by two feature
+    CLKIN_PERIOD => 31.25,         -- Specify period of input clock
+    CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+    CLK_FEEDBACK => "1X",       -- Specify clock feedback of NONE, 1X or 2X
+    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+    DFS_FREQUENCY_MODE => "LOW",            -- HIGH or LOW frequency mode for frequency synthesis
+    DLL_FREQUENCY_MODE => "LOW",            -- HIGH or LOW frequency mode for DLL
+    DUTY_CYCLE_CORRECTION => TRUE,          -- Duty cycle correction, TRUE or FALSE
+    FACTORY_JF => X"C080",                  -- FACTORY JF Values
+    PHASE_SHIFT => 0,                       -- Amount of fixed phase shift from -255 to 255
+    STARTUP_WAIT => FALSE                   -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+    ) 
+  port map (
+    CLK0 => clk0_b, -- 0 degree DCM CLK ouptput
+    CLK180 => open, -- 180 degree DCM CLK output
+    CLK270 => open, -- 270 degree DCM CLK output
+    CLK2X => open, -- 2X DCM CLK output
+    CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+    CLK90 => open, -- 90 degree DCM CLK output
+    CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+    CLKFX => dcmclock_b, -- DCM CLK synthesis out (M/D)
+    CLKFX180 => open, -- 180 degree CLK synthesis out
+    LOCKED => dcmlocked_b, -- DCM LOCK status output
+    PSDONE => open, -- Dynamic phase adjust done output
+    STATUS => open, -- 8-bit DCM status bits output
+    CLKFB => clkfb_b, -- DCM clock feedback
+    CLKIN => clkout_tmp, -- Clock input (from IBUFG, BUFG or DCM)
+    PSCLK => '0', -- Dynamic phase adjust clock input
+    PSEN => '0', -- Dynamic phase adjust enable input
+    PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
+    RST => '0' -- DCM asynchronous reset input
+  );
+
+
+
+end behave;

zpu/hdl/zpuino/boards/oho_godil/oho_godil.prj

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+vhdl work "zpu_config.vhd"
+vhdl work "../../zpupkg.vhd"
+vhdl work "zpuino_config.vhd"
+vhdl work "../../zpuinopkg.vhd"
+vhdl work "../../prescaler.vhd"
+vhdl work "../../uart_brgen.vhd"
+vhdl work "../../tx_unit.vhd"
+vhdl work "../../timer.vhd"
+vhdl work "../../spiclkgen.vhd"
+vhdl work "../../spi.vhd"
+vhdl work "../../zpuino_uart_rx.vhd"
+vhdl work "../../zpuino_uart_mv_filter.vhd"
+vhdl work "../../fifo.vhd"
+vhdl work "prom-generic-dp-32.vhd"
+vhdl work "stack.vhd"
+vhdl work "../../zpuino_uart.vhd"
+vhdl work "../../zpuino_timers.vhd"
+vhdl work "../../zpuino_spi.vhd"
+vhdl work "../../zpuino_sigmadelta.vhd"
+vhdl work "../../zpuino_intr.vhd"
+vhdl work "../../zpuino_gpio.vhd"
+vhdl work "../../zpuino_crc16.vhd"
+vhdl work "../../dualport_ram.vhd"
+vhdl work "../../wishbonepkg.vhd"
+vhdl work "../../zpu_core_extreme.vhd"
+vhdl work "../../wb_rom_ram.vhd"
+vhdl work "../../wbmux2.vhd"
+vhdl work "../../wbarb2_1.vhd"
+vhdl work "../../mult.vhd"
+vhdl work "../../shifter.vhd"
+vhdl work "../../zpuino_debug_core.vhd"
+vhdl work "../../zpuino_io.vhd"
+vhdl work "../../zpuino_top.vhd"
+vhdl work "../../zpuino_empty_device.vhd"
+vhdl work "../../zpuino_adc.vhd"
+vhdl work "../../zpuino_serialreset.vhd"
+vhdl work "../../pad.vhd"
+vhdl work "clkgen.vhd"
+vhdl work "oho_godil_top.vhd"

zpu/hdl/zpuino/boards/oho_godil/oho_godil.ut

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+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:25
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No

zpu/hdl/zpuino/boards/oho_godil/oho_godil.xst

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+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn oho_godil.prj
+-ifmt mixed
+-ofn oho_godil
+-ofmt NGC
+-p xc3s500e-4-vq100
+-top oho_godil_top
+-opt_mode Speed
+-opt_level 2
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints YES
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing NO
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing Yes
+-move_first_stage YES
+-move_last_stage YES
+-slice_packing YES
+-optimize_primitives YES
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5