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TinyTapeout · Apr 12, 2023 · 2796ef4 · 2796ef4
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diff --git a/.gitignore b/.gitignore
@@ -16,3 +16,7 @@ __pycache__
 scan_mux
 .DS_Store
 venv
+verilog/gl/all_sta.tcl
+verilog/gl/merged_user_project_wrapper.v
+verilog/gl/sta.sh
+verilog/gl/user_project_wrapper.v_edited
diff --git a/README.md b/README.md
@@ -23,7 +23,7 @@ For the most recent automatic build, click the tt_datasheet badge above, then do
 
 | Index | Author | Title | Type | Git Repo |
 | ----- | ------ | ------| -----| ---------|
-| 0 | Matt Venn | Test Inverter Project | [Wokwi](https://wokwi.com/projects/357464855584307201) | https://github.com/TinyTapeout/tt03-test-invert |
+| 0 | Matt Venn | Test Inverter Project | [Wokwi](https://wokwi.com/projects/361728533238569985) | https://github.com/TinyTapeout/tt03-test-invert |
 | 1 | Wallie Everest | ChipTune | HDL | https://github.com/WallieEverest/tt03 |
 | 2 | icegoat9 | 7 Segment Life | [Wokwi](https://wokwi.com/projects/357752736742764545) | https://github.com/icegoat9/tinytapeout03-7seglife |
 | 3 | Meinhard Kissich, EAS Group, Graz University of Technology | Another Piece of Pi | HDL | https://github.com/meiniKi/tt03-another-piece-of-pi |
@@ -57,3 +57,6 @@ For the most recent automatic build, click the tt_datasheet badge above, then do
 | 31 | yubex | tiny logic analyzer | HDL | https://github.com/yubex/tt03-tiny-logic-analyzer |
 | 32 | ReJ aka Renaldas Zioma | 4-bit ALU | [Wokwi](https://wokwi.com/projects/360745091952588801) | https://github.com/rejunity/tt03-alu-4bit |
 | 33 | Marco Merlin | Pulse-Density Modulators | HDL | https://github.com/bat52/tt03-ddpm-pwm |
+| 34 | Grant Hernandez (@grant-h) | CRC Decelerator | HDL | https://github.com/grant-h/tt03-crc-decelerator |
+| 35 | Matt Venn | 7 segment seconds | HDL | https://github.com/nikor/tt03-verilog-demo |
+| 36 | Norberto Hernandez-Como | Binary to DEC and HEX | [Wokwi](https://wokwi.com/projects/361684719151591425) | https://github.com/jedicomo22/Norberto_IPN_V1 |
diff --git a/datasheet.pdf b/datasheet.pdf
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
diff --git a/gds/diferential_muxpga.gds.gz b/gds/diferential_muxpga.gds.gz
diff --git a/gds/diferential_rvb1.gds.gz b/gds/diferential_rvb1.gds.gz
diff --git a/gds/granth_crc_decelerator.gds.gz b/gds/granth_crc_decelerator.gds.gz
diff --git a/gds/morningjava_top.gds.gz b/gds/morningjava_top.gds.gz
diff --git a/gds/nikor_clock.gds.gz b/gds/nikor_clock.gds.gz
diff --git a/gds/user_module_354091612057990145.gds.gz b/gds/user_module_354091612057990145.gds.gz
diff --git a/gds/user_module_360745091952588801.gds.gz b/gds/user_module_360745091952588801.gds.gz
diff --git a/gds/user_module_361684719151591425.gds.gz b/gds/user_module_361684719151591425.gds.gz
diff --git a/gds/user_module_361728533238569985.gds.gz b/gds/user_module_361728533238569985.gds.gz
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
diff --git a/gds/yubex_tiny_logic_analyzer.gds.gz b/gds/yubex_tiny_logic_analyzer.gds.gz
diff --git a/lef/diferential_muxpga.lef b/lef/diferential_muxpga.lef
@@ -179,45 +179,45 @@ MACRO diferential_muxpga
       LAYER li1 ;
         RECT 5.520 5.355 144.440 163.285 ;
       LAYER met1 ;
-        RECT 1.910 1.400 148.970 168.940 ;
+        RECT 0.070 0.380 149.890 168.600 ;
       LAYER met2 ;
-        RECT 0.090 0.155 148.950 168.970 ;
-      LAYER met3 ;
-        RECT 0.065 162.200 148.975 165.065 ;
-        RECT 2.400 160.800 148.975 162.200 ;
-        RECT 0.065 152.000 148.975 160.800 ;
-        RECT 2.400 150.600 148.975 152.000 ;
-        RECT 0.065 141.800 148.975 150.600 ;
-        RECT 2.400 140.400 148.975 141.800 ;
-        RECT 0.065 131.600 148.975 140.400 ;
-        RECT 2.400 130.200 148.975 131.600 ;
-        RECT 0.065 121.400 148.975 130.200 ;
-        RECT 2.400 120.000 148.975 121.400 ;
-        RECT 0.065 111.200 148.975 120.000 ;
-        RECT 2.400 109.800 148.975 111.200 ;
-        RECT 0.065 101.000 148.975 109.800 ;
-        RECT 2.400 99.600 148.975 101.000 ;
-        RECT 0.065 90.800 148.975 99.600 ;
-        RECT 2.400 89.400 148.975 90.800 ;
-        RECT 0.065 80.600 148.975 89.400 ;
-        RECT 2.400 79.200 148.975 80.600 ;
-        RECT 0.065 70.400 148.975 79.200 ;
-        RECT 2.400 69.000 148.975 70.400 ;
-        RECT 0.065 60.200 148.975 69.000 ;
-        RECT 2.400 58.800 148.975 60.200 ;
-        RECT 0.065 50.000 148.975 58.800 ;
-        RECT 2.400 48.600 148.975 50.000 ;
-        RECT 0.065 39.800 148.975 48.600 ;
-        RECT 2.400 38.400 148.975 39.800 ;
-        RECT 0.065 29.600 148.975 38.400 ;
-        RECT 2.400 28.200 148.975 29.600 ;
-        RECT 0.065 19.400 148.975 28.200 ;
-        RECT 2.400 18.000 148.975 19.400 ;
-        RECT 0.065 9.200 148.975 18.000 ;
-        RECT 2.400 7.800 148.975 9.200 ;
-        RECT 0.065 0.175 148.975 7.800 ;
+        RECT 0.100 0.155 149.870 168.630 ;
+      LAYER met3 ;
+        RECT 0.525 162.200 149.895 167.105 ;
+        RECT 2.400 160.800 149.895 162.200 ;
+        RECT 0.525 152.000 149.895 160.800 ;
+        RECT 2.400 150.600 149.895 152.000 ;
+        RECT 0.525 141.800 149.895 150.600 ;
+        RECT 2.400 140.400 149.895 141.800 ;
+        RECT 0.525 131.600 149.895 140.400 ;
+        RECT 2.400 130.200 149.895 131.600 ;
+        RECT 0.525 121.400 149.895 130.200 ;
+        RECT 2.400 120.000 149.895 121.400 ;
+        RECT 0.525 111.200 149.895 120.000 ;
+        RECT 2.400 109.800 149.895 111.200 ;
+        RECT 0.525 101.000 149.895 109.800 ;
+        RECT 2.400 99.600 149.895 101.000 ;
+        RECT 0.525 90.800 149.895 99.600 ;
+        RECT 2.400 89.400 149.895 90.800 ;
+        RECT 0.525 80.600 149.895 89.400 ;
+        RECT 2.400 79.200 149.895 80.600 ;
+        RECT 0.525 70.400 149.895 79.200 ;
+        RECT 2.400 69.000 149.895 70.400 ;
+        RECT 0.525 60.200 149.895 69.000 ;
+        RECT 2.400 58.800 149.895 60.200 ;
+        RECT 0.525 50.000 149.895 58.800 ;
+        RECT 2.400 48.600 149.895 50.000 ;
+        RECT 0.525 39.800 149.895 48.600 ;
+        RECT 2.400 38.400 149.895 39.800 ;
+        RECT 0.525 29.600 149.895 38.400 ;
+        RECT 2.400 28.200 149.895 29.600 ;
+        RECT 0.525 19.400 149.895 28.200 ;
+        RECT 2.400 18.000 149.895 19.400 ;
+        RECT 0.525 9.200 149.895 18.000 ;
+        RECT 2.400 7.800 149.895 9.200 ;
+        RECT 0.525 0.175 149.895 7.800 ;
       LAYER met4 ;
-        RECT 1.215 163.840 148.745 165.065 ;
+        RECT 1.215 163.840 149.665 165.065 ;
         RECT 1.215 4.800 21.685 163.840 ;
         RECT 24.085 4.800 39.050 163.840 ;
         RECT 41.450 4.800 56.415 163.840 ;
@@ -226,8 +226,8 @@ MACRO diferential_muxpga
         RECT 93.545 4.800 108.510 163.840 ;
         RECT 110.910 4.800 125.875 163.840 ;
         RECT 128.275 4.800 143.240 163.840 ;
-        RECT 145.640 4.800 148.745 163.840 ;
-        RECT 1.215 0.175 148.745 4.800 ;
+        RECT 145.640 4.800 149.665 163.840 ;
+        RECT 1.215 0.175 149.665 4.800 ;
   END
 END diferential_muxpga
 END LIBRARY

diff --git a/lef/granth_crc_decelerator.lef b/lef/granth_crc_decelerator.lef
@@ -0,0 +1,232 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO granth_crc_decelerator
+  CLASS BLOCK ;
+  FOREIGN granth_crc_decelerator ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 150.000 BY 170.000 ;
+  PIN io_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 8.200 2.000 8.800 ;
+    END
+  END io_in[0]
+  PIN io_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 18.400 2.000 19.000 ;
+    END
+  END io_in[1]
+  PIN io_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 28.600 2.000 29.200 ;
+    END
+  END io_in[2]
+  PIN io_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 38.800 2.000 39.400 ;
+    END
+  END io_in[3]
+  PIN io_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 49.000 2.000 49.600 ;
+    END
+  END io_in[4]
+  PIN io_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 59.200 2.000 59.800 ;
+    END
+  END io_in[5]
+  PIN io_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 69.400 2.000 70.000 ;
+    END
+  END io_in[6]
+  PIN io_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 79.600 2.000 80.200 ;
+    END
+  END io_in[7]
+  PIN io_out[0]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 89.800 2.000 90.400 ;
+    END
+  END io_out[0]
+  PIN io_out[1]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 100.000 2.000 100.600 ;
+    END
+  END io_out[1]
+  PIN io_out[2]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 110.200 2.000 110.800 ;
+    END
+  END io_out[2]
+  PIN io_out[3]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 120.400 2.000 121.000 ;
+    END
+  END io_out[3]
+  PIN io_out[4]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 130.600 2.000 131.200 ;
+    END
+  END io_out[4]
+  PIN io_out[5]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 140.800 2.000 141.400 ;
+    END
+  END io_out[5]
+  PIN io_out[6]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 151.000 2.000 151.600 ;
+    END
+  END io_out[6]
+  PIN io_out[7]
+    DIRECTION OUTPUT TRISTATE ;
+    USE SIGNAL ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 161.200 2.000 161.800 ;
+    END
+  END io_out[7]
+  PIN vccd1
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 22.085 5.200 23.685 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 56.815 5.200 58.415 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 91.545 5.200 93.145 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 126.275 5.200 127.875 163.440 ;
+    END
+  END vccd1
+  PIN vssd1
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 39.450 5.200 41.050 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 74.180 5.200 75.780 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 108.910 5.200 110.510 163.440 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 143.640 5.200 145.240 163.440 ;
+    END
+  END vssd1
+  OBS
+      LAYER li1 ;
+        RECT 5.520 5.355 144.440 163.285 ;
+      LAYER met1 ;
+        RECT 2.370 4.460 145.240 163.440 ;
+      LAYER met2 ;
+        RECT 2.390 4.235 145.210 163.385 ;
+      LAYER met3 ;
+        RECT 2.000 162.200 145.230 163.365 ;
+        RECT 2.400 160.800 145.230 162.200 ;
+        RECT 2.000 152.000 145.230 160.800 ;
+        RECT 2.400 150.600 145.230 152.000 ;
+        RECT 2.000 141.800 145.230 150.600 ;
+        RECT 2.400 140.400 145.230 141.800 ;
+        RECT 2.000 131.600 145.230 140.400 ;
+        RECT 2.400 130.200 145.230 131.600 ;
+        RECT 2.000 121.400 145.230 130.200 ;
+        RECT 2.400 120.000 145.230 121.400 ;
+        RECT 2.000 111.200 145.230 120.000 ;
+        RECT 2.400 109.800 145.230 111.200 ;
+        RECT 2.000 101.000 145.230 109.800 ;
+        RECT 2.400 99.600 145.230 101.000 ;
+        RECT 2.000 90.800 145.230 99.600 ;
+        RECT 2.400 89.400 145.230 90.800 ;
+        RECT 2.000 80.600 145.230 89.400 ;
+        RECT 2.400 79.200 145.230 80.600 ;
+        RECT 2.000 70.400 145.230 79.200 ;
+        RECT 2.400 69.000 145.230 70.400 ;
+        RECT 2.000 60.200 145.230 69.000 ;
+        RECT 2.400 58.800 145.230 60.200 ;
+        RECT 2.000 50.000 145.230 58.800 ;
+        RECT 2.400 48.600 145.230 50.000 ;
+        RECT 2.000 39.800 145.230 48.600 ;
+        RECT 2.400 38.400 145.230 39.800 ;
+        RECT 2.000 29.600 145.230 38.400 ;
+        RECT 2.400 28.200 145.230 29.600 ;
+        RECT 2.000 19.400 145.230 28.200 ;
+        RECT 2.400 18.000 145.230 19.400 ;
+        RECT 2.000 9.200 145.230 18.000 ;
+        RECT 2.400 7.800 145.230 9.200 ;
+        RECT 2.000 4.255 145.230 7.800 ;
+      LAYER met4 ;
+        RECT 9.495 4.800 21.685 159.625 ;
+        RECT 24.085 4.800 39.050 159.625 ;
+        RECT 41.450 4.800 56.415 159.625 ;
+        RECT 58.815 4.800 73.780 159.625 ;
+        RECT 76.180 4.800 91.145 159.625 ;
+        RECT 93.545 4.800 108.510 159.625 ;
+        RECT 110.910 4.800 125.875 159.625 ;
+        RECT 128.275 4.800 129.425 159.625 ;
+        RECT 9.495 4.255 129.425 4.800 ;
+  END
+END granth_crc_decelerator
+END LIBRARY
+
diff --git a/lef/morningjava_top.lef b/lef/morningjava_top.lef
@@ -179,9 +179,9 @@ MACRO morningjava_top
       LAYER li1 ;
         RECT 5.520 5.355 144.440 163.285 ;
       LAYER met1 ;
-        RECT 0.530 4.460 145.240 163.440 ;
+        RECT 2.370 5.200 145.240 163.440 ;
       LAYER met2 ;
-        RECT 0.560 4.430 145.210 163.385 ;
+        RECT 2.390 5.255 145.210 163.385 ;
       LAYER met3 ;
         RECT 2.000 162.200 145.230 163.365 ;
         RECT 2.400 160.800 145.230 162.200 ;
@@ -216,8 +216,6 @@ MACRO morningjava_top
         RECT 2.000 9.200 145.230 18.000 ;
         RECT 2.400 7.800 145.230 9.200 ;
         RECT 2.000 5.275 145.230 7.800 ;
-      LAYER met4 ;
-        RECT 49.055 6.295 49.385 69.185 ;
   END
 END morningjava_top
 END LIBRARY