verilog/rtl: Add more models to sky130_fd_sc_hd_fast.v

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
TinyTapeout · Apr 15, 2023 · 6b39c2e · 6b39c2e
1 parent eeefd8c
commit 6b39c2e
Showing 1 changed file with 55 additions and 0 deletions.
diff --git a/verilog/rtl/fast/sky130_fd_sc_hd_fast.v b/verilog/rtl/fast/sky130_fd_sc_hd_fast.v
@@ -498,6 +498,38 @@ module sky130_fd_sc_hd__buf_4(
 
 endmodule
 
+module sky130_fd_sc_hd__clkinv_2(
+    output wire Y   ,
+    input  wire A   ,
+    input  wire VPWR,
+    input  wire VGND,
+    input  wire VPB ,
+    input  wire VNB
+);
+
+    assign Y = ~A;
+
+    wire _unused;
+    assign _unused = &{ 1'b0, VPWR, VGND, VPB, VNB };
+
+endmodule
+
+module sky130_fd_sc_hd__clkinv_4(
+    output wire Y   ,
+    input  wire A   ,
+    input  wire VPWR,
+    input  wire VGND,
+    input  wire VPB ,
+    input  wire VNB
+);
+
+    assign Y = ~A;
+
+    wire _unused;
+    assign _unused = &{ 1'b0, VPWR, VGND, VPB, VNB };
+
+endmodule
+
 module sky130_fd_sc_hd__clkbuf_2(
     output wire X   ,
     input  wire A   ,
@@ -594,6 +626,29 @@ module sky130_fd_sc_hd__clkinv_1(
 
 endmodule
 
+module sky130_fd_sc_hd__dfrtp_4(
+    output reg  Q      ,
+    input  wire CLK    ,
+    input  wire D      ,
+    input  wire RESET_B,
+    input  wire VPWR   ,
+    input  wire VGND   ,
+    input  wire VPB    ,
+    input  wire VNB
+);
+
+    wire RESET = ~RESET_B;
+
+    always @(posedge CLK, posedge RESET) begin
+        if (RESET) Q <= 'd0;
+        else       Q <= D;
+    end
+
+    wire _unused;
+    assign _unused = &{ 1'b0, VPWR, VGND, VPB, VNB };
+
+endmodule
+
 module sky130_fd_sc_hd__dfrtn_1(
     output reg  Q      ,
     input  wire CLK_N  ,