feat: add info.yaml for all projects + index

project_info/AidanMedcalf_pid_controller/info.yaml

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+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+# wokwi id: 347889351946928723
+  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
+    - tt2.v
+    - pid.v
+    - spi_master_in.v
+    - spi_master_out.v
+    - spi_slave.v
+  top_module:  "AidanMedcalf_pid_controller"      # put the name of your top module here, make it unique by prepending your github username
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it.
+#
+# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
+#
+# This info will be automatically collected and used to make a datasheet for the chip.
+documentation: 
+  author:       "Aidan Medcalf"      # Your name
+  discord:      "Pomme de Terrible#1820"      # Your discord handle - make sure to include the # part as well
+  title:        "TinyPID"      # Project title
+  description:  "Tiny PID controller with SPI configuration channel, SPI ADC and DAC driver"      # Short description of what your project does
+  how_it_works: "TinyPID reads from a shift register, calculates error and PID values, and writes to a shift register. All parameters of this process are configurable."      # Longer description of how the project works
+  how_to_test:  "Shift in config, then shift in PV input and see what happens. There are three bytes of configuration (setpoint, kp, ki), which are zero on startup."      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  external_hw:  "One shift register / ADC for PV read, one shift register / DAC for stimulus output."       # Describe any external hardware needed
+  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  doc_link:     "https://github.com/AidanMedcalf/tt02-pid/blob/main/README.md"      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     1       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
+  picture:      ""      # relative path to a picture in your repository
+  inputs:               # a description of what the inputs do
+    - clock
+    - reset
+    - none
+    - cfg_clk
+    - cfg_mosi
+    - none
+    - cfg_cs
+    - pv_in_miso
+  outputs:
+    - pv_in_clk
+    - pv_in_cs
+    - out_clk
+    - out_mosi
+    - out_cs
+    - none
+    - none
+    - none
+

project_info/Asma_Mohsin_conv_enc_core/info.yaml

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+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
+     - Asma_Mohsin_conv_enc_core.v
+  top_module:  "Asma_Mohsin_conv_enc_core"      # put the name of your top module here, make it unique by prepending your github username
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it.
+#
+# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
+#
+# This info will be automatically collected and used to make a datasheet for the chip.
+documentation: 
+  author:       "Asma Mohsin"      # Your name
+  discord:      "Asma Mohsin#8645"      # Your discord handle - make sure to include the # part as well
+  title:        "channel coding"      # Project title
+  description:  "Convolutional coding is widely used in modern digital communication systems.We often get encoded data by using different polynomials having same constraint lengths (K)."      # Short description of what your project does
+  how_it_works: "We have two polynomials of 4th order and a shift register of 5 bits. we take input data of a single bit and put it in shift register on each clock edge as long as valid data bit is asserted. after this codeword is calculated by taking xor of the and of polynomial and shift register"      # Longer description of how the project works
+  how_to_test:  "apply clk,reset ,data valid and input data and do calculations to see if output is equal to the desired one"      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  external_hw:  ""      # Describe any external hardware needed
+  language:     "verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  doc_link:     "https://github.com/AsmaMohsin1507/tt02-channel-coding/blob/cccf2f01c80024d59eef60c292b57c8786c9e495/README.md"      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     6000      # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
+  picture:      ""      # relative path to a picture in your repository
+  inputs:               # a description of what the inputs do
+    - clock
+    - reset
+    - data valid
+    - data input
+    - none
+    - none
+    - none
+    - none
+  outputs:
+    - encoded data         # a description of what the outputs do
+    - none
+    - none
+    - none
+    - none
+    - none
+    - none
+    - none
+

project_info/BB_SYSTEM/info.yaml

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+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+
+# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
+# Source files must be in ./src and you must list each source file separately
+  source_files:        
+    - BB_SYSTEM.v
+    - SC_DEBOUNCE1.v
+    - SC_PSRANDOM.v
+    - SC_RegGENERAL.v
+    - SC_STATEMACHINE.v
+  top_module:  "BB_SYSTEM"      # put the name of your top module here, make it unique by prepending your github username
+
+# Keep a track of the submission yaml
+yaml_version: 3.0
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
+#
+# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
+documentation: 
+  author:       "CMUA F.Segura-Quijano, J.S.Moya"
+  title:        "PSRANDOM"
+  language:     "Verilog"
+  description:  "Pseudo Random generator."
+
+# Longer description of how the project works. You can use standard markdown format.
+  how_it_works: |
+      Uses a General Register controled with a State Machine with a Pseudo Random Generator Circuit. 
+
+      Puts a pseudo random data un wave output bus.
+
+# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  how_to_test:  |
+      After reset, push load o rand buttom. Load change one time data out bus. Rand change continius data out bus.
+
+# A description of what the inputs do
+  inputs:               
+    - BB_SYSTEM_CLOCK_50
+    - BB_SYSTEM_RESET_InHigh
+    - BB_SYSTEM_loadseed_InLow
+    - BB_SYSTEM_loaddata_InLow
+    - BB_SYSTEM_rand_InLow
+    - BB_SYSTEM_data_InBUS[0]
+    - BB_SYSTEM_data_InBUS[1]
+    - BB_SYSTEM_data_InBUS[2]
+# A description of what the outputs do
+  outputs:
+    - BB_SYSTEM_data_OutBUS[7]
+    - BB_SYSTEM_data_OutBUS[6]
+    - BB_SYSTEM_data_OutBUS[5]
+    - BB_SYSTEM_data_OutBUS[4]
+    - BB_SYSTEM_data_OutBUS[3]
+    - BB_SYSTEM_data_OutBUS[2]
+    - BB_SYSTEM_data_OutBUS[1]
+    - BB_SYSTEM_data_OutBUS[0]
+
+# The following fields are optional
+  tag:          "timer, test"      # comma separated list of tags: test encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  external_hw:  ""      # Describe any external hardware needed
+  discord:      ""      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     1000       # Clock frequency in Hz (if required)
+  picture:      ""      # relative path to a picture in your repository

project_info/BenAtUvu_combo/info.yaml

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+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+
+# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
+# Source files must be in ./src and you must list each source file separately
+  source_files:
+    - combolock.v
+  top_module:  "BenAtUvu_combo"      # put the name of your top module here, make it unique by prepending your github username
+
+# Keep a track of the submission yaml
+yaml_version: 3.0
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
+#
+# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
+documentation: 
+  author:       "Benjamin Collier"      # Your name
+  title:        "Combo lock"      # Project title
+  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  description:  "set, reset, and check for a combo"      # Short description of what your project does
+
+# Longer description of how the project works. You can use standard markdown format.
+  how_it_works: |
+      this projects works by taking 4 inputs for number 0-9. The first 4 number inputed will be the new combo (0000 is not an input zero should be 0001). 
+      Then to "unlock" press your combo again. to reset and enter a new combo the unlock must be high and reset must be pressed, or master reset must be pressed.
+      
+
+# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  how_to_test:  |
+      Enter 4 single digits in binary into input 0-4, each input must be followed by 0000. Then input the same 4 digits in each followed by 0000 to make unlock high. 
+      a valid input would look some think like this: 0001, 0000, 0101, 0000, 1001, 0000, 0011, 0000, then 0001, 0000, 0101, 0000, 1001, 0000, 0011, 0000, will make
+      unlock high.
+
+# A description of what the inputs do
+  inputs:               
+    - input 0
+    - input 1
+    - input 2
+    - input 3
+    - reset
+    - master reset
+    - none
+    - none
+# A description of what the outputs do
+  outputs:
+    - unlock
+    - none
+    - none
+    - none
+    - none
+    - none
+    - none
+    - none
+
+# The following fields are optional
+  tag:          ""      # comma separated list of tags: test encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  external_hw:  ""      # Describe any external hardware needed
+  discord:      ""      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     0       # Clock frequency in Hz (if required)
+  picture:      ""      # relative path to a picture in your repository

project_info/FSM_LAT/info.yaml

@@ -0,0 +1,71 @@
+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
+    - FSM_LAT.v
+    - FSM.v
+    - clk_sel.v
+    - clock_div.v
+    - clock_divider.v
+    - SIPO.v
+    - dff_5.v
+    - d_ff.v
+    - desition.v
+    - chaout.v
+    - Comparador.v
+    - counter.v
+    - registro20bits.v
+    - jk_ff.v
+    - mux2_1.v
+    - PISO.v
+    - piso_1_bit.v
+    - PISO_div.v
+    - ring_osc.v
+    - inv_with_delay.v
+    - inv_with_delay_16.v
+    - nand2_with_delay.v
+    #
+
+  top_module:  "FSM_LAT"      # put the name of your top module here, make it unique by prepending your github username
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it.
+#
+# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
+#
+# This info will be automatically collected and used to make a datasheet for the chip.
+documentation: 
+  author:       "Juan Sanchez"      # Your name
+  discord:      "juander28#1964"      # Your discord handle
+  title:        "FSM_LAT"      # Project title
+  description:  "FSM look at table"      # Short description of what your project does
+  how_it_works: "el proyecto es una maquina de estados a la cual se le puede cambiar la secuencia de los estados por medio de una entrada serial "      # Longer description of how the project works
+  how_to_test:  "para cagar la secuencnia de estados se debe conectar un relog el cual este sincronixado con la secuencia serial para programar la maquina de estados = y para pasar de estado la entrada conectada a cada estado debe estar en 1"      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  external_hw:  "un fpga que permita generar un relog una salida serial para programar la secuencia de la maquina de estados "      # Describe any external hardware needed
+  language:     "verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     0       # Clock frequency in Hz (if required)
+  picture:      ""      # relative path to a picture in your repository
+  inputs:             # a description of what the inputs do
+
+# A description of what the outputs do
+  inputs:             # a description of what the inputs do
+    - oi_in[0]
+    - oi_in[1]
+    - oi_in[2]
+    - oi_in[3]
+    - oi_in[4]
+    - oi_in[5]
+    - oi_in[6]
+    - oi_in[7]
+  outputs:
+    - oi_out[1]
+    - oi_out[2]
+    - oi_out[3]
+    - oi_out[4]
+    - oi_out[5]
+    - oi_out[6]
+    - oi_out[7]
+    - oi_out[0]
+

project_info/HiddenRoom_HiddenCPU/info.yaml

@@ -0,0 +1,88 @@
+--- 
+# TinyTapeout project information
+project:
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+
+# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
+# Source files must be in ./src and you must list each source file separately
+  source_files:        
+    - top.v
+    - decode.v
+    - mux.v
+    - ALU.v
+    - add.v
+    - sub.v
+    - xor.v
+    - movAndBranch.v
+  top_module:  "HiddenRoom_HiddenCPU"      # put the name of your top module here, make it unique by prepending your github username
+
+# Keep a track of the submission yaml
+yaml_version: 3.0
+
+# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
+# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
+#
+# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
+documentation: 
+  author:       "HiddenRoom"
+  title:        "HiddenCPU"
+  language:     "Verilog"
+  description:  "Basic 8 bit CPU."
+
+# Longer description of how the project works. You can use standard markdown format.
+  how_it_works: |
+      Each instruction is executed in one clock cycle.
+
+      Instructions are inputed on io_in[2:7].
+
+  instruction_format: |
+      io_in[2:3] = opcode (00 add, 01 sub, 10 xor, 11 mov or special operations)
+      io_in[4:5] = result reg address
+      io_in[6:7] = operand reg address
+
+      Special operations are executed when the register address in a mov instruction are the same. These would normally acts as a nop but are instead repurposed as follows
+      register address    special operation
+      00                  add r3 to pc if 
+                          carryflag is high
+
+      01                  memWrite r3 into
+                          address r2
+
+      10                  memRead address r2
+                          into r3
+
+      11                  swap output between
+                          pc and r3
+
+# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  how_to_test:  |
+      After reset, registers will initialize, in order of ascending address, to 00000000b, 00000001b, 00000010b, 00000011b
+
+# A description of what the inputs do
+  inputs:               
+    - clock
+    - reset
+    - opcode bit zero
+    - opcode bit one
+    - result reg address bit zero
+    - result reg address bit one
+    - non result operand reg address bit zero
+    - non result operand reg address bit one
+# A description of what the outputs do
+  outputs:
+    - bit zero of hardwired output reg number at address 11b or pc 
+    - bit one of hardwired output reg number at address 11b or pc 
+    - bit two of hardwired output reg number at address 11b or pc 
+    - bit three of hardwired output reg number at address 11b or pc 
+    - bit four of hardwired output reg number at address 11b or pc 
+    - bit five of hardwired output reg number at address 11b or pc 
+    - bit six of hardwired output reg number at address 11b or pc 
+    - bit seven of hardwired output reg number at address 11b or pc 
+
+# The following fields are optional
+  tag:          "risc, microprocessor, alu"      # comma separated list of tags: test encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  external_hw:  "No absolute requirements but external memory and hardware for addressing is not a bad idea"      # Describe any external hardware needed
+  discord:      "ComedyMan#6380"      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
+  clock_hz:     1000       # Clock frequency in Hz (if required)
+  picture:      ""      # relative path to a picture in your repository