docs: Update docs for all three tt_um_toivoh_basilisc_2816 variants (#…

…238)

projects/tt_um_toivoh_basilisc_2816/info.yaml

@@ -1,6 +1,6 @@
 # Tiny Tapeout project information
 project:
-  title:        "Basilisc-2816"      # Project title
+  title:        "Basilisc-2816 v0.1a CPU"      # Project title
   author:       "Toivo Henningsson"      # Your name
   discord:      "possible_realities"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Small 2-bit serial 8/16 bit CPU"      # One line description of what your project does
@@ -42,7 +42,7 @@ pinout:
   uo[0]: "tx_out[0]"
   uo[1]: "tx_out[1]"
   uo[2]: "tx_fetch"
-  uo[3]: ""
+  uo[3]: "tx_jump"
   uo[4]: ""
   uo[5]: ""
   uo[6]: ""

projects/tt_um_toivoh_basilisc_2816_cpu_OL2/docs/info.md

@@ -7,34 +7,66 @@ You can also include images in this folder and reference them in the markdown. E
 512 kb in size, and the combined size of all images must be less than 1 MB.
 -->
 
+![](combined.png)
+
 ## Overview
 
 Basilisc-2816 v0.1 is a small 2-bit serial 2/8/16 bit processor that fits into one Tiny Tapeout tile.
-The CPU has been designed around the constraints of
+It has been designed around the constraints of
 
 - small area,
-- 4 pin serial memory interface to a RAM emulator implemented in a RP2040 microcontroller, which can be supported by the RP2040 microcontroller on the Tiny Tapeout 06 Demo Board.
-
-and a later version is intended to be included in the next version of the AnemoneGrafx-8 retro console https://github.com/toivoh/tt06-retro-console (motivating the constraints).
+- 4 pin serial memory interface to a RAM emulator implemented in an RP2040 microcontroller (which can be supported by the RP2040 microcontroller on the Tiny Tapeout 7 Demo Board),
+- to be suitable to be included in in the next version of the AnemoneGrafx-8 retro console https://github.com/toivoh/tt06-retro-console, which motivates the other constraints.
 
 Features:
 
 - 2-bit serial execution:
-	- ALU operations etc are calculated 2 bits/cycle
-	- 2-bit-serial register file with two read/write ports realized as a bank of shift registers
-	- Saves area compared to processing 8/16 bits per cycle
+	- ALU results etc are calculated at 2 bits/cycle
+	- 2-bit-serial register file with two read/write ports
+	- Addresses and data are sent to/from memory at 2 bits/cycle
+		- The processor starts to operate on each bit of incoming read data as it arrives
+	- Saves area compared to processing 8/16 bits per cycle / using a parallel access register file
 	- No point in calculating faster than the memory interface allows
-- 8x 8-bit registers that can be paired into 4x 16-bit registers
-- 16 bits/instruction (some instructions might take an additional 16 bit immediate)
+- 8x 8-bit general purpose registers that can be paired into 4x 16-bit general purpose registers, plus an 8 bit stack register
+- 8 bit and 16 bit versions of almost all instructions
 - 64 kB address space
-- Quite regular and orthogonal instruction encoding
-- Many addressing modes
-- Variable shift instructions
-- 8x8 and 8x16 bit multiply instructions, producing 2 result bits per cycle like everything else
-- 13 branch conditions + relative call
-- Instruction prefetch queue
+- 16 bits/instruction
+- Quite regular and orthogonal instruction encoding, most instructions can use most addressing modes
+	- `op reg, src` and `op src, reg` instruction forms
+- Instructions:
+	- `mov`, `swap`
+	- `binop`: `add/adc/sub/sbc/and/or/xor/cmp/test`
+		- for register-to-register also: `neg/negc/revsub/revsbc/and_not/`
+		  `or_not/xor_not/not`,
+	- `shl/shr/sar/rol/ror` with variable or immediate shift count,
+	- `mul`: 8x8 and 8x16 bit multiply instructions, producing 2 result bits per cycle like everything else,
+	- `branch cc, offset`: relative branch
+		- unconditional/call/12 conditions including signed/unsigned comparisons,
+	- `jump/call`: absolut direct/indirect jump/call,
+	- additional functionality through combination with addressing modes, e g, `ret = jump [pop]`
+- Addressing modes:
+	- `[imm7]` / `[imm7*2]`: zero page
+	- `[r16 + imm2]`
+	- `[r16 + r8]`
+	- `[r16]` with postincrement/predecrement
+	- `[push]` / `[pop]` / `[top-of-stack]` depending on whether the operand is written/read/modified
+	- `[imm16]`
+- Sign/zero extension of any 8 bit register as source operand to 16 bit instructions
+- `imm16` / `[imm16]` operands supported using extra instruction word
+- 2-4 word instruction prefetch queue
+
+## Basilisc-2816 v0.1 variants
+
+Basilisc-2816 v0.1 has been taped out in three variants for Tiny Tapeout 7:
+
+	        mul           Prefetch     Hardened     Uses      Mux
+	        instruction   queue size   with         latches   address
+	v0.1a           yes            2   OpenLane 1        no       967
+	v0.1b            no            3   OpenLane 2        no       202
+	v0.1c           yes            4   OpenLane 2       yes        72
 
-This is the v0.1b version, which is hardened using OpenLane 2, omits the `mul` instruction, but has a prefetch queue of 3 instruction words.
-The v0.1a version `tt_um_toivoh_basilisc_2816` can be found at https://github.com/toivoh/tt07-basilisc-2816-cpu.
+successively more experimental. Longer prefetch queue should help contribute to better performance,
+especially with long memory access latencies.
 
-For more details, see https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md or the documentation of `tt_um_toivoh_basilisc_2816`.
+This is the 0.1b version.
+For more details, see https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md or the documentation for Basilisc-2816 v0.1a CPU [967].

projects/tt_um_toivoh_basilisc_2816_cpu_OL2/info.yaml

@@ -1,6 +1,6 @@
 # Tiny Tapeout project information
 project:
-  title:        "Basilisc-2816"      # Project title
+  title:        "Basilisc-2816 v0.1b CPU"      # Project title
   author:       "Toivo Henningsson"      # Your name
   discord:      "possible_realities"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Small 2-bit serial 8/16 bit CPU"      # One line description of what your project does
@@ -15,10 +15,12 @@ project:
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
+    - "delay_buffer.v"
     - "regfile.v"
     - "alu.v"
     - "scheduler.v"
     - "decoder.v"
+    - "latch_register.v"
     - "fifos.v"
     - "sb_io.v"
     - "mem_interface.v"

projects/tt_um_toivoh_basilisc_2816_cpu_exp/docs/info.md

@@ -7,42 +7,66 @@ You can also include images in this folder and reference them in the markdown. E
 512 kb in size, and the combined size of all images must be less than 1 MB.
 -->
 
+![](combined.png)
+
 ## Overview
 
 Basilisc-2816 v0.1 is a small 2-bit serial 2/8/16 bit processor that fits into one Tiny Tapeout tile.
-The CPU has been designed around the constraints of
+It has been designed around the constraints of
 
 - small area,
-- 4 pin serial memory interface to a RAM emulator implemented in a RP2040 microcontroller, which can be supported by the RP2040 microcontroller on the Tiny Tapeout 06 Demo Board.
-
-and a later version is intended to be included in the next version of the AnemoneGrafx-8 retro console https://github.com/toivoh/tt06-retro-console (motivating the constraints).
+- 4 pin serial memory interface to a RAM emulator implemented in an RP2040 microcontroller (which can be supported by the RP2040 microcontroller on the Tiny Tapeout 7 Demo Board),
+- to be suitable to be included in in the next version of the AnemoneGrafx-8 retro console https://github.com/toivoh/tt06-retro-console, which motivates the other constraints.
 
 Features:
 
 - 2-bit serial execution:
-	- ALU operations etc are calculated 2 bits/cycle
-	- 2-bit-serial register file with two read/write ports realized as a bank of shift registers
-	- Saves area compared to processing 8/16 bits per cycle
+	- ALU results etc are calculated at 2 bits/cycle
+	- 2-bit-serial register file with two read/write ports
+	- Addresses and data are sent to/from memory at 2 bits/cycle
+		- The processor starts to operate on each bit of incoming read data as it arrives
+	- Saves area compared to processing 8/16 bits per cycle / using a parallel access register file
 	- No point in calculating faster than the memory interface allows
-- 8x 8-bit registers that can be paired into 4x 16-bit registers
-- 16 bits/instruction (some instructions might take an additional 16 bit immediate)
+- 8x 8-bit general purpose registers that can be paired into 4x 16-bit general purpose registers, plus an 8 bit stack register
+- 8 bit and 16 bit versions of almost all instructions
 - 64 kB address space
-- Quite regular and orthogonal instruction encoding
-- Many addressing modes
-- Variable shift instructions
-- 8x8 and 8x16 bit multiply instructions, producing 2 result bits per cycle like everything else
-- 13 branch conditions + relative call
-- Instruction prefetch queue
+- 16 bits/instruction
+- Quite regular and orthogonal instruction encoding, most instructions can use most addressing modes
+	- `op reg, src` and `op src, reg` instruction forms
+- Instructions:
+	- `mov`, `swap`
+	- `binop`: `add/adc/sub/sbc/and/or/xor/cmp/test`
+		- for register-to-register also: `neg/negc/revsub/revsbc/and_not/`
+		  `or_not/xor_not/not`,
+	- `shl/shr/sar/rol/ror` with variable or immediate shift count,
+	- `mul`: 8x8 and 8x16 bit multiply instructions, producing 2 result bits per cycle like everything else,
+	- `branch cc, offset`: relative branch
+		- unconditional/call/12 conditions including signed/unsigned comparisons,
+	- `jump/call`: absolut direct/indirect jump/call,
+	- additional functionality through combination with addressing modes, e g, `ret = jump [pop]`
+- Addressing modes:
+	- `[imm7]` / `[imm7*2]`: zero page
+	- `[r16 + imm2]`
+	- `[r16 + r8]`
+	- `[r16]` with postincrement/predecrement
+	- `[push]` / `[pop]` / `[top-of-stack]` depending on whether the operand is written/read/modified
+	- `[imm16]`
+- Sign/zero extension of any 8 bit register as source operand to 16 bit instructions
+- `imm16` / `[imm16]` operands supported using extra instruction word
+- 2-4 word instruction prefetch queue
+
+## Basilisc-2816 v0.1 variants
 
-This is the v0.1c experimental version, which
+Basilisc-2816 v0.1 has been taped out in three variants for Tiny Tapeout 7:
 
-- is hardened using OpenLane 2,
-- uses latches for the prefetch queue and instruction register,
-- includes the `mul` instruction, and
-- has a prefetch queue of 4 instruction words.
+	        mul           Prefetch     Hardened     Uses      Mux
+	        instruction   queue size   with         latches   address
+	v0.1a           yes            2   OpenLane 1        no       967
+	v0.1b            no            3   OpenLane 2        no       202
+	v0.1c           yes            4   OpenLane 2       yes        72
 
-The usage of latches is experimental, but allows to pack in more features.
-The v0.1a version can be found at https://github.com/toivoh/tt07-basilisc-2816-cpu.
-The v0.1b version can be found at https://github.com/toivoh/tt07-basilisc-2816-cpu-OL2.
+successively more experimental. Longer prefetch queue should help contribute to better performance,
+especially with long memory access latencies.
 
-For more details, see https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md or the documentation of `tt_um_toivoh_basilisc_2816`.
+This is the 0.1c version.
+For more details, see https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md or the documentation for Basilisc-2816 v0.1a CPU [967].

projects/tt_um_toivoh_basilisc_2816_cpu_exp/info.yaml

@@ -1,6 +1,6 @@
 # Tiny Tapeout project information
 project:
-  title:        "Basilisc-2816 Experimental"      # Project title
+  title:        "Basilisc-2816 v0.1c CPU (experimental)"      # Project title
   author:       "Toivo Henningsson"      # Your name
   discord:      "possible_realities"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Small 2-bit serial 8/16 bit CPU"      # One line description of what your project does