Updated readme and speed grader for MiST to 8

Torlus · Apr 7, 2017 · 4030331 · 4030331
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diff --git a/README.txt b/README.txt
@@ -3,10 +3,9 @@ MiST, Turbo Chameleon 64, Altera/Terasic DE2 board
 
 The core shall be considered a work in progress as there are multiple issues:
 1. Sprite flickering on heavy scenes, or on large sprites
-2. No sound yet, the Z80 is in but not any sound chip
+2. No LFO modulation of the FM sound
 3. Rom file formats supported are .bin and .gen, no support for .smd files
-4. 15 kHz video mode not supported yet, only VGA works
-5. The design does not fit on the Altera/Terasic DE1 board anymore
+4. The design does not fit on the Altera/Terasic DE1 board anymore
 
 ==== Installing the core ====
 If you are not buidling the core, copy the following files to the root of your sdcard:
@@ -27,7 +26,7 @@ fpgagen/syn/mist/fpgagen.qpf
 
 When you have built the core, copy the following files to the root of your sdcard:
 fpgagen/syn/mist/fpgagen.rbf
-fpgagen/Configs/VGA/FPGAGEN.CFG
+fpgagen/Configs/VGA/FPGAGEN.CFG, or fpgagen/Configs/TV/FPGAGEN.CFG (for 15 kHz video)
 
 Then rename the file fpgagen.rbf to core.rbf
 

diff --git a/syn/mist/fpgagen.pin b/syn/mist/fpgagen.pin
@@ -63,8 +63,8 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP  "fpgagen"  ASSIGNED TO AN: EP3C25E144C7
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "fpgagen"  ASSIGNED TO AN: EP3C25E144C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
@@ -82,12 +82,12 @@ SDRAM_A[8]                   : 11        : output : 3.3-V LVTTL       :
 RESERVED_INPUT_WITH_WEAK_PULLUP : 12        :        :                   :         : 1         :                
 CONF_DATA0                   : 13        : input  : 3.3-V LVTTL       :         : 1         : Y              
 nCONFIG                      : 14        :        :                   :         : 1         :                
-altera_reserved_tdi          : 15        : input  : 3.3-V LVTTL       :         : 1         : N              
-altera_reserved_tck          : 16        : input  : 3.3-V LVTTL       :         : 1         : N              
+TDI                          : 15        : input  :                   :         : 1         :                
+TCK                          : 16        : input  :                   :         : 1         :                
 VCCIO1                       : 17        : power  :                   : 3.3V    : 1         :                
-altera_reserved_tms          : 18        : input  : 3.3-V LVTTL       :         : 1         : N              
+TMS                          : 18        : input  :                   :         : 1         :                
 GND                          : 19        : gnd    :                   :         :           :                
-altera_reserved_tdo          : 20        : output : 3.3-V LVTTL       :         : 1         : N              
+TDO                          : 20        : output :                   :         : 1         :                
 nCE                          : 21        :        :                   :         : 1         :                
 GND+                         : 22        :        :                   :         : 1         :                
 GND+                         : 23        :        :                   :         : 1         :