Converts 32-bit binary to a seven-segment display floating point format using a state machine in System Verilog. The number of seven-segment display digits can vary from a minimum of 6 digits up to 60+ digits. For more information, check out: TristonBabers.com/floating-point-convertor.
Simulation: ModelSim - INTEL FPGA STARTER EDITION 10.5b [download]
Synthesis: Quartus Prime 22.1std Lite Edition [download]
- To setup ModelSim for synthesis, make a new project containing the SystemVerilog files in the verilog folder.
- Run the simulation using the toplevel_tb.sv file as the test bench, and the results will appear in the same directory in "output_file.txt".
- For synthesis, use top_level.sv as the highest level module, and pick the ARIA II board option in the new project wizard.
Source code is licensed under the MIT license.