Kotsu2Risc

SystemVerilog implementation of RISC-V ISA for FPGA.

content

Now RV64I and part of RV64M are implemented.(Priviledged modes are not yet)

• src : SystemVerilog sources
• test : test codes

architecture

For simplicity as the first project, this RISCV processor has single cycle architecture, and instruction memory and data memory are seperated.

test code

test.dat was assembled from test.S. test.S is a translation of the MIPS test code (mipstest.asm, written by David Harris and Sarah Harris) for RISCV.

future work

• test codes for other instructions
• supporting priviledged modes and interrupts
• supporting division, atomic operations, etc...
  • this inevitably requires multi-cycle architecture
• unify data memory and instruction memory (using built-in DRAM)