Based on code here https://github.com/UDXS/hdl-vlsi-exprs/tree/master/ASQRT
Copyright (C) 2022 Davit Margarian
Licensed under Apache 2.0
(Original readme for the template repository here)
This repo is an experiment in using Verilog source files instead of Wokwi diagrams for TinyTapeout, implementing a 5-bit PDM driver.
The Verilog flow is:
- Fork this Repo
- Create a wokwi project to get an ID
- Update WOWKI_PROJECT_ID in Makefile
grep -rl "341154068332282450" ./src | sed -i "s/341154068332282450/YOUR_WOKWI_ID/g"
from the top of the repo to find and replace all occurences of the old ID insrc
with yours, and rename theuser_module
,user_module_tb
andscan_wrapper
files to use your ID- Replace behavioural code in user_module_ID.v with your own, likewise change the testbench
- Push changes, which triggers the GitHub Action to build the project