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Function pipelining requires to unroll all loops in the function and sub-functions. When calculating the II of the function pipeline, IIs of all sub-functions also need to be considered.
The complicated part of dataflow pragma estimation is the latency of two dataflow stages can be overlapped when the intermediate buffer between them can be implemented as FIFO. This decision is automatically made by Vivado HLS possibly based on the loop order. Some concrete case studies may help us to better understand the mechanism under the hood.
For now, we are simply accumulating latencies of all dataflow stages to calculate the overall latency.
Function pipeline insertion, estimation; FIFO dataflow estimation.
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