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Intel ACPI Component Architecture
ACPI Binary Table Extraction Utility version 20200925
Copyright (c) 2000 - 2020 Intel Corporation
Signature Length Version Oem Oem Oem Compiler Compiler
Id TableId RevisionId Name Revision
_________ __________ ____ ________ __________ __________ _______ __________
01) APIC 0x00000068 0x01 "PTLTD " " APIC " 0x06040000 " LTP" 0x00000000
02) SSDT 0x000000A6 0x01 "PmRef " "Cpu1Tst " 0x00003000 "INTL" 0x20050624
03) MCFG 0x0000003C 0x01 "INTEL " "CRESTLNE" 0x06040000 "LOHR" 0x0000005A
04) SLIC 0x00000176 0x01 "ITINFO" " " 0x06040000 "LOHR" 0x0000005A
05) SSDT 0x00000079 0x01 "BrtRef" "DD01BRT " 0x00001000 "INTL" 0x20050624
06) BOOT 0x00000028 0x01 "PTLTD " "$SBFTBL$" 0x06040000 " LTP" 0x00000001
07) DSDT 0x00006565 0x02 "INTEL " "CRESTLNE" 0x06040000 "INTL" 0x20050624
08) SSDT 0x000004E6 0x01 "PmRef " "CpuPm " 0x00003000 "INTL" 0x20050624
09) TMOR 0x00000026 0x01 "PTLTD " " " 0x06040000 "PTL " 0x00000003
10) APIC 0x00000068 0x01 "INTEL " "CRESTLNE" 0x06040000 "LOHR" 0x0000005A
11) SSDT 0x0000025F 0x01 "PmRef " "Cpu0Tst " 0x00003000 "INTL" 0x20050624
12) FACP 0x000000F4 0x03 "INTEL " "CRESTLNE" 0x06040000 "ALAN" 0x00000001
13) SSDT 0x000002AD 0x01 "SataRe" "SataAhci" 0x00001000 "INTL" 0x20050624
14) TCPA 0x00000032 0x01 "Intel " " CRESTLN" 0x06040000 " LOH" 0x00005A52
15) HPET 0x00000038 0x01 "INTEL " "CRESTLNE" 0x06040000 "LOHR" 0x0000005A
16) FACS 0x00000040 0x01
17) SSDT 0x00000085 0x01 "PmRef " "Cpu1Cst " 0x00003000 "INTL" 0x20050624
18) SSDT 0x0000065E 0x01 "PmRef " "Cpu0Cst " 0x00003001 "INTL" 0x20050624
19) SSDT 0x000000C8 0x01 "PmRef " "Cpu1Ist " 0x00003000 "INTL" 0x20050624
20) SSDT 0x0000027A 0x01 "PmRef " "Cpu0Ist " 0x00003000 "INTL" 0x20050624
Found 20 ACPI tables in acpidump
APIC1
-----
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
[004h 0004 4] Table Length : 00000068
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : 13
[00Ah 0010 6] Oem ID : "PTLTD "
[010h 0016 8] Oem Table ID : " APIC "
[018h 0024 4] Oem Revision : 06040000
[01Ch 0028 4] Asl Compiler ID : " LTP"
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
[035h 0053 1] Length : 08
[036h 0054 1] Processor ID : 01
[037h 0055 1] Local Apic ID : 01
[038h 0056 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[03Ch 0060 1] Subtable Type : 01 [I/O APIC]
[03Dh 0061 1] Length : 0C
[03Eh 0062 1] I/O Apic ID : 02
[03Fh 0063 1] Reserved : 00
[040h 0064 4] Address : FEC00000
[044h 0068 4] Interrupt : 00000000
[048h 0072 1] Subtable Type : 04 [Local APIC NMI]
[049h 0073 1] Length : 06
[04Ah 0074 1] Processor ID : 00
[04Bh 0075 2] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
[04Dh 0077 1] Interrupt Input LINT : 01
[04Eh 0078 1] Subtable Type : 04 [Local APIC NMI]
[04Fh 0079 1] Length : 06
[050h 0080 1] Processor ID : 01
[051h 0081 2] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
[053h 0083 1] Interrupt Input LINT : 01
[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
[055h 0085 1] Length : 0A
[056h 0086 1] Bus : 00
[057h 0087 1] Source : 00
[058h 0088 4] Interrupt : 00000002
[05Ch 0092 2] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
[05Fh 0095 1] Length : 0A
[060h 0096 1] Bus : 00
[061h 0097 1] Source : 09
[062h 0098 4] Interrupt : 00000009
[066h 0102 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
Raw Table Data: Length 104 (0x68)
0000: 41 50 49 43 68 00 00 00 01 13 50 54 4C 54 44 20 // APICh.....PTLTD
0010: 09 20 41 50 49 43 20 20 00 00 04 06 20 4C 54 50 // . APIC .... LTP
0020: 00 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 02 00 // ................
0040: 00 00 C0 FE 00 00 00 00 04 06 00 05 00 01 04 06 // ................
0050: 01 05 00 01 02 0A 00 00 02 00 00 00 05 00 02 0A // ................
0060: 00 09 09 00 00 00 0D 00 // ........
APIC2
-----
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
[004h 0004 4] Table Length : 00000068
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : CC
[00Ah 0010 6] Oem ID : "INTEL "
[010h 0016 8] Oem Table ID : "CRESTLNE"
[018h 0024 4] Oem Revision : 06040000
[01Ch 0028 4] Asl Compiler ID : "LOHR"
[020h 0032 4] Asl Compiler Revision : 0000005A
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
[035h 0053 1] Length : 08
[036h 0054 1] Processor ID : 01
[037h 0055 1] Local Apic ID : 01
[038h 0056 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[03Ch 0060 1] Subtable Type : 01 [I/O APIC]
[03Dh 0061 1] Length : 0C
[03Eh 0062 1] I/O Apic ID : 01
[03Fh 0063 1] Reserved : 00
[040h 0064 4] Address : FEC00000
[044h 0068 4] Interrupt : 00000000
[048h 0072 1] Subtable Type : 02 [Interrupt Source Override]
[049h 0073 1] Length : 0A
[04Ah 0074 1] Bus : 00
[04Bh 0075 1] Source : 00
[04Ch 0076 4] Interrupt : 00000002
[050h 0080 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
[052h 0082 1] Subtable Type : 02 [Interrupt Source Override]
[053h 0083 1] Length : 0A
[054h 0084 1] Bus : 00
[055h 0085 1] Source : 09
[056h 0086 4] Interrupt : 00000009
[05Ah 0090 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
[05Ch 0092 1] Subtable Type : 04 [Local APIC NMI]
[05Dh 0093 1] Length : 06
[05Eh 0094 1] Processor ID : 00
[05Fh 0095 2] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
[061h 0097 1] Interrupt Input LINT : 01
[062h 0098 1] Subtable Type : 04 [Local APIC NMI]
[063h 0099 1] Length : 06
[064h 0100 1] Processor ID : 01
[065h 0101 2] Flags (decoded below) : 0005
Polarity : 1
Trigger Mode : 1
[067h 0103 1] Interrupt Input LINT : 01
Raw Table Data: Length 104 (0x68)
0000: 41 50 49 43 68 00 00 00 01 CC 49 4E 54 45 4C 20 // APICh.....INTEL
0010: 43 52 45 53 54 4C 4E 45 00 00 04 06 4C 4F 48 52 // CRESTLNE....LOHR
0020: 5A 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // Z...............
0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 01 00 // ................
0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
0050: 00 00 02 0A 00 09 09 00 00 00 0D 00 04 06 00 05 // ................
0060: 00 01 04 06 01 05 00 01 // ........
BOOT
----
[000h 0000 4] Signature : "BOOT" [Simple Boot Flag Table]
[004h 0004 4] Table Length : 00000028
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : A5
[00Ah 0010 6] Oem ID : "PTLTD "
[010h 0016 8] Oem Table ID : "$SBFTBL$"
[018h 0024 4] Oem Revision : 06040000
[01Ch 0028 4] Asl Compiler ID : " LTP"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Boot Register Index : 36
[025h 0037 3] Reserved : 000000
Raw Table Data: Length 40 (0x28)
0000: 42 4F 4F 54 28 00 00 00 01 A5 50 54 4C 54 44 20 // BOOT(.....PTLTD
0010: 24 53 42 46 54 42 4C 24 00 00 04 06 20 4C 54 50 // $SBFTBL$.... LTP
0020: 01 00 00 00 36 00 00 00 // ....6...
DSDT
----
DefinitionBlock ("", "DSDT", 2, "INTEL ", "CRESTLNE", 0x06040000)
{
External (_PR_.CPU0._PPC, UnknownObj)
External (CFGD, UnknownObj)
External (PDC0, UnknownObj)
External (PDC1, UnknownObj)
Mutex (MUTX, 0x00)
OperationRegion (PRT0, SystemIO, 0x80, 0x04)
Field (PRT0, DWordAcc, Lock, Preserve)
{
P80H, 32
}
Method (P8XH, 2, Serialized)
{
If ((Arg0 == Zero))
{
P80D = ((P80D & 0xFFFFFF00) | Arg1)
}
If ((Arg0 == One))
{
P80D = ((P80D & 0xFFFF00FF) | (Arg1 << 0x08))
}
If ((Arg0 == 0x02))
{
P80D = ((P80D & 0xFF00FFFF) | (Arg1 << 0x10))
}
If ((Arg0 == 0x03))
{
P80D = ((P80D & 0x00FFFFFF) | (Arg1 << 0x18))
}
P80H = P80D /* \P80D */
}
Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
{
GPIC = Arg0
}
Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep
{
P80D = Zero
P8XH (Zero, Arg0)
Local1 = (\_SB.PCI0.LPCB.PMRD (0xB5) & 0xF7)
\_SB.PCI0.LPCB.PMWT (0xB5, Local1)
If ((Arg0 == 0x03))
{
Local3 = (\_SB.PCI0.LPCB.PMRD (0xF2) & One)
If (Local3) {}
Else
{
Local1 = (\_SB.PCI0.LPCB.PMRD (0xB8) & 0xFE)
\_SB.PCI0.LPCB.PMWT (0xB8, Local1)
}
}
If ((Arg0 == 0x05)) {}
TRAP (0x67)
TRAP (0x50)
}
Method (_WAK, 1, NotSerialized) // _WAK: Wake
{
P8XH (One, 0xAB)
If (((Arg0 == 0x03) || (Arg0 == 0x04)))
{
If ((CFGD & 0x01000000))
{
If (((CFGD & 0xF0) && (OSYS == 0x07D1)))
{
TRAP (0x3D)
}
}
}
If ((RP1D == Zero))
{
Notify (\_SB.PCI0.RP01, Zero) // Bus Check
}
If ((RP2D == Zero))
{
Notify (\_SB.PCI0.RP02, Zero) // Bus Check
}
If ((RP3D == Zero))
{
Notify (\_SB.PCI0.RP03, Zero) // Bus Check
}
If ((RP4D == Zero))
{
Notify (\_SB.PCI0.RP04, Zero) // Bus Check
}
If ((RP5D == Zero))
{
Notify (\_SB.PCI0.RP05, Zero) // Bus Check
}
If ((RP6D == Zero))
{
Notify (\_SB.PCI0.RP06, Zero) // Bus Check
}
If ((Arg0 == 0x03))
{
Local3 = (\_SB.PCI0.LPCB.PMRD (0xF2) & One)
If (Local3)
{
\_SB.PCI0.LPCB.PMWT (0xF2, Zero)
}
Else
{
Local1 = (\_SB.PCI0.LPCB.PMRD (0xB8) | One)
\_SB.PCI0.LPCB.PMWT (0xB8, Local1)
\_SB.PCI0.LPCB.PMWT (0xF2, Zero)
}
TRAP (0x46)
}
If ((Arg0 == 0x04))
{
If (DTSE)
{
TRAP (0x47)
}
Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
Notify (\_SB.PWRB, 0x02) // Device Wake
}
\_PR.RPPC ()
Local1 = (\_SB.PCI0.LPCB.PMRD (0xB5) | 0x08)
\_SB.PCI0.LPCB.PMWT (0xB5, Local1)
LIDS = One
\_SB.PCI0.GFX0.GLID (LIDS)
\_SB.LID.LIDF = One
Notify (\_SB.LID, 0x80) // Status Change
P8XH (Zero, 0xCD)
Return (Package (0x02)
{
Zero,
Zero
})
}
Method (GETB, 3, Serialized)
{
Local0 = (Arg0 * 0x08)
Local1 = (Arg1 * 0x08)
CreateField (Arg2, Local0, Local1, TBF3)
Return (TBF3) /* \GETB.TBF3 */
}
Method (PNOT, 0, Serialized)
{
If (MPEN)
{
If ((PDC0 & 0x08))
{
Notify (\_PR.CPU0, 0x80) // Performance Capability Change
If ((PDC0 & 0x10))
{
Sleep (0x64)
Notify (\_PR.CPU0, 0x81) // C-State Change
}
}
If ((PDC1 & 0x08))
{
Notify (\_PR.CPU1, 0x80) // Performance Capability Change
If ((PDC1 & 0x10))
{
Sleep (0x64)
Notify (\_PR.CPU1, 0x81) // C-State Change
}
}
}
Else
{
Notify (\_PR.CPU0, 0x80) // Performance Capability Change
Sleep (0x64)
Notify (\_PR.CPU0, 0x81) // C-State Change
}
}
Method (TRAP, 1, Serialized)
{
SMIF = Arg0
TRP0 = Zero
Return (SMIF) /* \SMIF */
}
Scope (_SB)
{
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
If (DTSE)
{
TRAP (0x47)
}
OSYS = 0x07D0
If (CondRefOf (_OSI, Local0))
{
If (_OSI ("Linux"))
{
LINX = One
}
If (_OSI ("Windows 2001"))
{
OSYS = 0x07D1
}
If (_OSI ("Windows 2001 SP1"))
{
OSYS = 0x07D1
}
If (_OSI ("Windows 2001 SP2"))
{
OSYS = 0x07D2
}
If (_OSI ("Windows 2006"))
{
OSYS = 0x07D6
}
}
If ((MPEN && (OSYS == 0x07D1)))
{
TRAP (0x3D)
}
TRAP (0x2B)
TRAP (0x32)
If (IGDS)
{
LIDS = One
^PCI0.GFX0.GLID (LIDS)
}
}
}
OperationRegion (GNVS, SystemMemory, 0xBF6DEDBC, 0x0100)
Field (GNVS, AnyAcc, Lock, Preserve)
{
OSYS, 16,
SMIF, 8,
PRM0, 8,
PRM1, 8,
SCIF, 8,
PRM2, 8,
PRM3, 8,
LCKF, 8,
PRM4, 8,
PRM5, 8,
P80D, 32,
LIDS, 8,
PWRS, 8,
DBGS, 8,
LINX, 8,
Offset (0x14),
ACT1, 8,
ACTT, 8,
PSVT, 8,
TC1V, 8,
TC2V, 8,
TSPV, 8,
CRTT, 8,
DTSE, 8,
DTS1, 8,
DTS2, 8,
Offset (0x28),
APIC, 8,
MPEN, 8,
PCP0, 8,
PCP1, 8,
PPCM, 8,
Offset (0x32),
Offset (0x3C),
IGDS, 8,
TLST, 8,
CADL, 8,
PADL, 8,
CSTE, 16,
NSTE, 16,
SSTE, 16,
NDID, 8,
DID1, 32,
DID2, 32,
DID3, 32,
DID4, 32,
DID5, 32,
Offset (0x67),
BLCS, 8,
BRTL, 8,
ALSE, 8,
ALAF, 8,
LLOW, 8,
LHIH, 8,
Offset (0x6E),
EMAE, 8,
EMAP, 16,
EMAL, 16,
Offset (0x74),
MEFE, 8,
Offset (0x78),
TPMP, 8,
TPME, 8,
Offset (0x82),
GTF0, 56,
GTF2, 56,
IDEM, 8,
GTF1, 56,
Offset (0xAA),
ASLB, 32,
IBTT, 8,
IPAT, 8,
ITVF, 8,
ITVM, 8,
IPSC, 8,
IBLC, 8,
IBIA, 8,
ISSC, 8,
I409, 8,
I509, 8,
I609, 8,
I709, 8,
IDMM, 8,
IDMS, 8,
IF1E, 8,
HVCO, 8,
NXD1, 32,
NXD2, 32,
NXD3, 32,
NXD4, 32,
NXD5, 32,
NXD6, 32,
NXD7, 32,
NXD8, 32,
OSCC, 8,
OSCS, 8,
NEXP, 8,
Offset (0xE6),
BRLV, 8
}
Name (DSEN, One)
Name (ECON, Zero)
Name (GPIC, Zero)
Name (CTYP, Zero)
Name (L01C, Zero)
Name (VFN0, Zero)
Name (VFN1, Zero)
Scope (_GPE)
{
Mutex (GLCK, 0x00)
Method (_L01, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
L01C += One
P8XH (Zero, One)
P8XH (One, L01C)
If (((RP1D == Zero) && \_SB.PCI0.RP01.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP01.PDCX)
{
\_SB.PCI0.RP01.PDCX = One
\_SB.PCI0.RP01.HPSX = One
Notify (\_SB.PCI0.RP01, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP01.HPSX = One
}
}
If (((RP2D == Zero) && \_SB.PCI0.RP02.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP02.PDCX)
{
\_SB.PCI0.RP02.PDCX = One
\_SB.PCI0.RP02.HPSX = One
Notify (\_SB.PCI0.RP02, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP02.HPSX = One
}
}
If (((RP3D == Zero) && \_SB.PCI0.RP03.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP03.PDCX)
{
\_SB.PCI0.RP03.PDCX = One
\_SB.PCI0.RP03.HPSX = One
Notify (\_SB.PCI0.RP03, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP03.HPSX = One
}
}
If (((RP4D == Zero) && \_SB.PCI0.RP04.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP04.PDCX)
{
\_SB.PCI0.RP04.PDCX = One
\_SB.PCI0.RP04.HPSX = One
Notify (\_SB.PCI0.RP04, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP04.HPSX = One
}
}
If (((RP5D == Zero) && \_SB.PCI0.RP05.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP05.PDCX)
{
\_SB.PCI0.RP05.PDCX = One
\_SB.PCI0.RP05.HPSX = One
Notify (\_SB.PCI0.RP05, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP05.HPSX = One
}
}
If (((RP6D == Zero) && \_SB.PCI0.RP06.HPSX))
{
Sleep (0x64)
If (\_SB.PCI0.RP06.PDCX)
{
\_SB.PCI0.RP06.PDCX = One
\_SB.PCI0.RP06.HPSX = One
Notify (\_SB.PCI0.RP06, Zero) // Bus Check
}
Else
{
\_SB.PCI0.RP06.HPSX = One
}
}
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L02, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
GPEC = Zero
Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
}
Method (_L03, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.USB1, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L04, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.USB2, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L05, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.USB5, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L06, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
If (\_SB.PCI0.GFX0.GSSE)
{
\_SB.PCI0.GFX0.GSCI ()
}
Else
{
SCIS = One
}
}
Method (_L07, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
\_SB.PCI0.SBUS.HSTS = 0x20
}
Method (_L08, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Acquire (GLCK, 0xFFFF)
Local0 = \_SB.PCI0.LPCB.PMRD (0xA8)
Local1 = \_SB.PCI0.LPCB.PMRD (0xA9)
Local2 = \_SB.PCI0.LPCB.PMRD (0xAA)
If (Local3 = (Local0 & One))
{
\_SB.LID.LIDF = One
Notify (\_SB.LID, 0x80) // Status Change
Local4 = \_SB.PCI0.LPCB.PMRD (0xB8)
Local5 = \_SB.PCI0.LPCB.PMRD (0xB7)
Local4 &= 0xFE
\_SB.PCI0.LPCB.PMWT (0xB8, Local4)
If ((\_SB.PCI0.LPCB.PMRD (0xB5) & One))
{
Local7 = \_SB.PCI0.LPCB.PMRD (0xB7)
Local7 &= 0xFE
\_SB.PCI0.LPCB.PMWT (0xB7, Local7)
\_SB.PCI0.LPCB.PMWT (0xF2, Zero)
\_SB.LID.LIDF = One
}
Else
{
Local7 = \_SB.PCI0.LPCB.PMRD (0xB7)
Local7 |= One
\_SB.PCI0.LPCB.PMWT (0xB7, Local7)
\_SB.PCI0.LPCB.PMWT (0xF2, One)
\_SB.LID.LIDF = Zero
}
Local6 = \_SB.PCI0.LPCB.PMRD (0xA8)
Local6 &= 0xFE
\_SB.PCI0.LPCB.PMWT (0xA8, Local6)
Local4 |= One
\_SB.PCI0.LPCB.PMWT (0xB8, Local4)
Notify (\_SB.LID, 0x80) // Status Change
}
Local7 = (\_SB.PCI0.LPCB.PMRD (0xAC) & 0xEF)
\_SB.PCI0.LPCB.PMWT (0xAC, Local7)
Release (GLCK)
}
Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
If (\_SB.PCI0.RP01.PSPX)
{
\_SB.PCI0.RP01.PSPX = One
\_SB.PCI0.RP01.PMSX = One
Notify (\_SB.PCI0.RP01, 0x02) // Device Wake
}
If (\_SB.PCI0.RP02.PSPX)
{
\_SB.PCI0.RP02.PSPX = One
\_SB.PCI0.RP02.PMSX = One
Notify (\_SB.PCI0.RP02, 0x02) // Device Wake
}
If (\_SB.PCI0.RP03.PSPX)
{
\_SB.PCI0.RP03.PSPX = One
\_SB.PCI0.RP03.PMSX = One
Notify (\_SB.PCI0.RP03, 0x02) // Device Wake
}
If (\_SB.PCI0.RP04.PSPX)
{
\_SB.PCI0.RP04.PSPX = One
\_SB.PCI0.RP04.PMSX = One
Notify (\_SB.PCI0.RP04, 0x02) // Device Wake
}
If (\_SB.PCI0.RP05.PSPX)
{
\_SB.PCI0.RP05.PSPX = One
\_SB.PCI0.RP05.PMSX = One
Notify (\_SB.PCI0.RP05, 0x02) // Device Wake
}
If (\_SB.PCI0.RP06.PSPX)
{
\_SB.PCI0.RP06.PSPX = One
\_SB.PCI0.RP06.PMSX = One
Notify (\_SB.PCI0.RP06, 0x02) // Device Wake
}
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.PCIB, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L0C, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.USB3, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L0D, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
If (\_SB.PCI0.EHC1.PMES)
{
\_SB.PCI0.EHC1.PMES = One
Notify (\_SB.PCI0.EHC1, 0x02) // Device Wake
}
If (\_SB.PCI0.EHC2.PMES)
{
\_SB.PCI0.EHC2.PMES = One
Notify (\_SB.PCI0.EHC2, 0x02) // Device Wake
}
If (\_SB.PCI0.HDEF.PMES)
{
\_SB.PCI0.HDEF.PMES = One
Notify (\_SB.PCI0.HDEF, 0x02) // Device Wake
}
}
Method (_L0E, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Notify (\_SB.PCI0.USB4, 0x02) // Device Wake
Notify (\_SB.PWRB, 0x02) // Device Wake
}
Method (_L18, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF
{
Acquire (GLCK, 0xFFFF)
Local0 = \_SB.PCI0.LPCB.PMRD (0xAB)
Local7 = \_SB.PCI0.LPCB.PMRD (0xAF)
Local3 = (Local7 & 0x04)
If ((Local3 != Zero))
{
\_SB.PCI0.LPCB.PMMW (0x01E8, Zero)
}
If (Local3 = (Local7 & One))
{
Local5 = (\_SB.PCI0.LPCB.PMRD (0xAD) & 0xFE)
\_SB.PCI0.LPCB.PMWT (0xAD, Local5)
Local5 = (\_SB.PCI0.LPCB.PMRD (0xAE) & 0xFE)
\_SB.PCI0.LPCB.PMWT (0xAE, Local5)
Local5 = (\_SB.PCI0.LPCB.PMRD (0xAF) & 0xFC)
\_SB.PCI0.LPCB.PMWT (0xAF, Local5)
Notify (\_TZ.TZ00, 0x80) // Thermal Status Change
}
If (Local3 = (Local0 & One))
{
Local2 = (\_SB.PCI0.LPCB.PMRD (0xAB) & 0xFE)
\_SB.PCI0.LPCB.PMWT (0xAB, Local2)
PWRS = (\_SB.PCI0.LPCB.PMRD (0xA0) & One)
TRAP (0x5A)
Notify (\_SB.ACAD, 0x80) // Status Change
TRAP (0x2B)
PNOT ()
}
If (Local3 = (Local0 & 0x02))
{
Notify (\_SB.ACAD, 0x80) // Status Change
Local1 = \_SB.PCI0.LPCB.PMRD (0xA1)
Local4 = \_SB.PCI0.LPCB.PMRD (0xF1)
If (((Local3 = (Local1 & One)) != (Local5 = (Local4 & One))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x81) // Information Change
}
If (((Local3 = (Local1 & 0x02)) != (Local5 = (Local4 & 0x02))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x04)) != (Local5 = (Local4 & 0x04))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x08)) != (Local5 = (Local4 & 0x08))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x10)) != (Local5 = (Local4 & 0x10))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x20)) != (Local5 = (Local4 & 0x20))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x40)) != (Local5 = (Local4 & 0x40))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
If (((Local3 = (Local1 & 0x80)) != (Local5 = (Local4 & 0x80))))
{
Local6 = \_SB.PCI0.LPCB.PMRD (0xA1)
\_SB.PCI0.LPCB.PMWT (0xF1, Local6)
Notify (\_SB.BAT0, 0x80) // Status Change
}
Local2 = (\_SB.PCI0.LPCB.PMRD (0xAB) & 0xFD)
\_SB.PCI0.LPCB.PMWT (0xAB, Local2)
}
Release (GLCK)
}
}
Scope (_PR)
{
Processor (CPU0, 0x00, 0x00001010, 0x06) {}
Processor (CPU1, 0x01, 0x00001010, 0x06) {}
Method (RPPC, 0, NotSerialized)
{
If ((OSYS == 0x07D2))
{
If ((CFGD & One))
{
If ((^CPU0._PPC > Zero))
{
^CPU0._PPC -= One
PNOT ()
^CPU0._PPC += One
PNOT ()
}
Else
{
^CPU0._PPC += One
PNOT ()
^CPU0._PPC -= One
PNOT ()
}
}
}
}
}
Scope (_TZ)
{
PowerResource (FN00, 0x00, 0x0000)
{
Method (_STA, 0, Serialized) // _STA: Status
{
Return (VFN0) /* \VFN0 */
}