fix ay when turbo mode enabled

Some ay chips (mostly early ones?) stuttered when cpu frequency (and control signals timings) were too fast for them.
UzixLS · Jul 30, 2022 · c26baf8 · c26baf8
1 parent 12c070f
commit c26baf8
Show file tree

Hide file tree

Showing 3 changed files with 19 additions and 10 deletions.
diff --git a/cpld/rtl/ay.sv b/cpld/rtl/ay.sv
@@ -10,7 +10,8 @@ module ay(
     output reg ay_clk,
     output reg ay_bc1,
     output reg ay_bdir,
-    output d_out_active
+    output d_out_active,
+    output cpuwait
 );
 
 //              bdir bc1 description
@@ -28,12 +29,14 @@ always @(posedge clk28 or negedge rst_n) begin
     else begin
         if (ck35)
             ay_clk <= ~ay_clk;
-        ay_bc1  <= en && bus.a[15] == 1'b1 && bus.a[14] == 1'b1 && bus.a[1] == 0 && bus.ioreq;
-        ay_bdir <= en && bus.a[15] == 1'b1 && bus.a[1] == 0 && bus.ioreq && bus.wr;
+        // bus.iorq used instead of bus.ioreq for faster response (important for turbo modes)
+        ay_bc1  <= en && bus.a[15] == 1'b1 && bus.a[14] == 1'b1 && bus.a[1] == 0 && bus.iorq && !bus.m1;
+        ay_bdir <= en && bus.a[15] == 1'b1 && bus.a[1] == 0 && bus.iorq && !bus.m1 && bus.wr;
     end
 end
 
 assign d_out_active = !ay_bdir && ay_bc1;
+assign cpuwait = ay_bc1 | ay_bdir;
 
 
 endmodule
diff --git a/cpld/rtl/cpucontrol.sv b/cpld/rtl/cpucontrol.sv
@@ -16,7 +16,8 @@ module cpucontrol(
     input [2:0] rampage128,
     input machine_t machine,
     input turbo_t turbo,
-    input ext_wait_cycle,
+    input ext_wait_cycle1,
+    input ext_wait_cycle2,
 
     output reg n_rstcpu_out,
     output reg clkcpu,
@@ -45,22 +46,24 @@ assign snow = bus.a[14] && ~bus.a[15] && bus.rfsh && (machine == MACHINE_S48 ||
 
 
 /* CLOCK */
-reg [3:0] turbo_wait;
+reg [5:0] turbo_wait;
 wire turbo_wait_trig0 = turbo == TURBO_14 && bus.mreq && !bus.rfsh;
 wire turbo_wait_trig1 = turbo == TURBO_14 && (bus.rd || bus.wr);
 reg turbo_wait_trig0_prev, turbo_wait_trig1_prev;
 always @(posedge clk28) begin
     turbo_wait[0] <= turbo_wait_trig0 && !turbo_wait_trig0_prev;
     turbo_wait[1] <= turbo_wait[0] || (turbo_wait_trig1 && !turbo_wait_trig1_prev);
-    turbo_wait[2] <= turbo_wait[1] && (bus.iorq || ext_wait_cycle);
+    turbo_wait[2] <= turbo_wait[1] && (bus.iorq || ext_wait_cycle1);
     turbo_wait[3] <= turbo_wait[2];
+    turbo_wait[4] <= turbo_wait[3] && ext_wait_cycle2;
+    turbo_wait[5] <= turbo_wait[4];
     turbo_wait_trig0_prev <= turbo_wait_trig0;
     turbo_wait_trig1_prev <= turbo_wait_trig1;
 end
 
 reg clkcpu_prev;
 assign clkcpu_ck = clkcpu && !clkcpu_prev;
-assign clkwait = contention || (|turbo_wait[3:1]);
+assign clkwait = contention || (|turbo_wait[5:1]);
 always @(posedge clk28) begin
     clkcpu_prev <= clkcpu;
     if (clkwait)
@@ -92,7 +95,7 @@ wire int_begin =
         vc == INT_V_S128 && hc == INT_H_S128 :
     // Pentagon
         vc == INT_V_PENT && hc == INT_H_PENT ;
-        
+
 reg [4:0] int_cnt;
 assign n_int_next = (|int_cnt)? 1'b0 : 1'b1;
 always @(posedge clk28 or negedge rst_n) begin

diff --git a/cpld/rtl/top.sv b/cpld/rtl/top.sv
@@ -88,6 +88,7 @@ wire magic_reboot, magic_beeper;
 wire up_active;
 wire clkwait;
 wire [2:0] rampage128;
+wire ay_wait;
 wire div_wait;
 wire sd_indication;
 wire bright_boost;
@@ -293,7 +294,8 @@ cpucontrol cpucontrol0(
     .machine(machine),
     .screen_contention(screen_contention),
     .turbo(turbo),
-    .ext_wait_cycle(div_wait),
+    .ext_wait_cycle1(ay_wait || div_wait),
+    .ext_wait_cycle2(ay_wait),
 
     .n_rstcpu_out(n_rstcpu_out),
     .clkcpu(clkcpu),
@@ -428,7 +430,8 @@ ay ay0(
     .ay_clk(ay_clk),
     .ay_bc1(ay_bc1),
     .ay_bdir(ay_bdir),
-    .d_out_active(ay_dout_active)
+    .d_out_active(ay_dout_active),
+    .cpuwait(ay_wait)
 );