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Sourcecode <bus/stream/stream_Buffer.vhdl>Testbench <bus/stream/stream_Buffer_tb.vhdl>
This module implements a generic buffer (FIFO) for the PoC.Stream </Interfaces/Stream> protocol. It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for data and meta information.
Entity Declaration:
../../../../src/bus/stream/stream_Buffer.vhdl
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Source file: bus/stream/stream_Buffer.vhdl <bus/stream/stream_Buffer.vhdl>