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ddr3_mem2mig_adapter_Series7.rst

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PoC.mem.ddr3.mem2mig_adapter_Series7

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GitHub Links

  • Sourcecode <mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl>
  • Testbench <mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl>

Adapter between the PoC.Mem <INT:PoC.Mem> interface and the application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs.

Simplifies the application interface ("app") of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found here <INT:PoC.Mem>.

Generic parameters:

  • D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one word in bits.
  • DQ_BITS: Size of data bus between memory controller and external memory (DIMM, SoDIMM).
  • MEM_A_BITS: Address bus width of the PoC.Mem interface.
  • APP_A_BTIS: Address bus width of the "app" interface.

Containts only combinational logic.

Entity Declaration:

../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl

latex

Source file: mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl <mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl>