Fix axi_lite_master wait behaviour if idle

vunit/vhdl/verification_components/src/axi_lite_master.vhd

@@ -50,6 +50,7 @@ end entity;
 
 architecture a of axi_lite_master is
   constant reply_queue, message_queue : queue_t := new_queue;
+  signal idle : boolean := true;
 begin
   main : process
     variable request_msg : msg_t;
@@ -61,7 +62,9 @@ begin
     if is_read(msg_type) or is_write(msg_type) then
       push(message_queue, request_msg);
     elsif msg_type = wait_until_idle_msg then
-      wait until ((bvalid and bready) = '1' or (rvalid and rready) = '1') and is_empty(message_queue) and rising_edge(aclk);
+      if not idle or not is_empty(message_queue) then
+        wait until idle and is_empty(message_queue) and rising_edge(aclk);
+      end if;
       handle_wait_until_idle(net, msg_type, request_msg);
     else
       unexpected_msg_type(msg_type);
@@ -76,6 +79,8 @@ begin
     variable expected_resp : axi_resp_t;
   begin
     wait until rising_edge(aclk) and not is_empty(message_queue);
+    idle <= false;
+    wait for 0 ps;
 
     request_msg := pop(message_queue);
     msg_type := message_type(request_msg);
@@ -137,6 +142,8 @@ begin
                 " to address 0x" & to_hstring(awaddr));
       end if;
     end if;
+
+    idle <= true;
   end process;
 
   -- Reply in separate process do not destroy alignment with the clock

vunit/vhdl/verification_components/test/tb_axi_lite_master.vhd

@@ -58,6 +58,7 @@ begin
   main : process
     variable tmp : std_logic_vector(rdata'range);
     variable rnd : RandomPType;
+    variable timestamp : time;
   begin
     test_runner_setup(runner, runner_cfg);
     rnd.InitSeed("common_seed");
@@ -119,6 +120,24 @@ begin
                          rnd.RandSlv(axi_resp_t'length));
         end if;
       end loop;
+
+    elsif run("Test idle when idle") then
+      wait until rising_edge(clk);
+      write_bus(net, bus_handle, x"01234567", x"1122");
+      wait for 0 ps;
+      timestamp := now;
+      wait_until_idle(net, bus_handle);
+      check(now > timestamp, "Write: First wait did not have to wait");
+      timestamp := now;
+      wait_until_idle(net, bus_handle);
+      check_equal(timestamp, now, "Write: Second wait had to wait");
+
+      wait until rising_edge(clk);
+      read_bus(net, bus_handle, x"01234567", tmp);
+      timestamp := now;
+      wait_until_idle(net, bus_handle);
+      check_equal(timestamp, now, "Read: Second wait had to wait");
+
     end if;
 
     wait for 100 ns;
@@ -367,6 +386,42 @@ begin
         end if;
       end loop;
       done <= true;
+
+    elsif enabled("Test idle when idle") then
+      wait until rising_edge(clk);
+      awready <= '1';
+      wait until (awready and awvalid) = '1' and rising_edge(clk);
+      awready <= '0';
+      check_equal(awaddr, std_logic_vector'(x"01234567"), "awaddr");
+
+      wait until rising_edge(clk);
+      wready <= '1';
+      wait until (wready and wvalid) = '1' and rising_edge(clk);
+      wready <= '0';
+      check_equal(wdata, std_logic_vector'(x"1122"), "wdata");
+      check_equal(wstrb, std_logic_vector'("11"), "wstrb");
+
+      wait until rising_edge(clk);
+      bvalid <= '1';
+      bresp <= axi_resp_okay;
+      wait until (bready and bvalid) = '1' and rising_edge(clk);
+      bvalid <= '0';
+
+      wait until rising_edge(clk);
+      arready <= '1';
+      wait until (arready and arvalid) = '1' and rising_edge(clk);
+      arready <= '0';
+      check_equal(araddr, std_logic_vector'(x"01234567"), "araddr");
+
+      wait until rising_edge(clk);
+      rvalid <= '1';
+      rresp <= axi_resp_okay;
+      rdata <= x"5566";
+      wait until (rready and rvalid) = '1' and rising_edge(clk);
+      rvalid <= '0';
+
+      done <= true;
+
     end if;
   end process;