parsing: allow multiply and divide within component instantiations (#966

) Co-authored-by: Kim Taylor <kimt@blackmagicdesign.com>
VUnit · Mar 13, 2024 · deef9d3 · deef9d3
1 parent 86007a4
commit deef9d3
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diff --git a/docs/news.d/966.feature.rst b/docs/news.d/966.feature.rst
@@ -0,0 +1 @@
+Allow multiply and divide within component instantiations.
diff --git a/vunit/vhdl_parser.py b/vunit/vhdl_parser.py
@@ -86,7 +86,7 @@ def parse(cls, code):
 
     _component_re = re.compile(
         r"[a-zA-Z]\w*\s*\:\s*(?:component)?\s*(?:(?:[a-zA-Z]\w*)\.)?([a-zA-Z]\w*)\s*"
-        r"(?:generic|port) map\s*\([\s\w\=\>\,\.\)\(\+\-\'\"]*\);",
+        r"(?:generic|port) map\s*\([\s\w\=\>\,\.\)\(\+\-\*\/\'\"]*\);",
         re.IGNORECASE,
     )