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Include free verilog compiler #188
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Some work has been done by @ehliar. Not sure about current status. Join https://gitter.im/VUnit/vunit to find out |
Any news? |
No, not really. This is an area where we would appreciate contributions. Have you been able to work on this @ehliar? |
Did someone get a response from @ehliar about his initial steps? (https://gitter.im/VUnit/vunit/archives/2016/04/27). I am interested in having the |
I made some attempt. I've a crude version running. However it is only skeleton as Icarus has issues around SV string methods, copy etc. I would like to support especially if there is some spec on what it takes to run a unit test under VUnit - like there is setup, loop etc. I believe it is obvious for SW folks, not so popular for HW engineers I guess. I've been hacking the unit_pkg files with those APIs - making them skeleton and uncommenting line-by-line. I feel that spoils the core functionality at some point as there are work-arounds for Icarus. Is there a doc for the VUNIT API from a developer perspective? Thanks |
@svenka3 Would it be possible to make your work public so that everyone interested can help out? The starting point for our documentation is VUnit.github.io. There you'll find how to use VUnit but there is no documentation for the details needed to develop the tool. The only information we have is how to make sure that the things you've made doesn't break anything. http://vunit.github.io/contributing.html |
Sure, will upload. Please give me few days to do so. |
Quick update - I believe I now have the "loop" function ported to Icarus. Looks like Icarus support for string is minimal and hence the remaining 2 functions: setup() and search_replace() seem unlikely to run on it. Can you please clarify what you would like to achieve via the setup()? I am sure we can find a pure Verilog way of doing it. Search-Replace - good for future maybe! Thanks |
Please see: https://github.com/svenka3/vunit_icarus Please do let me know if you see any issue in running it. As I cautioned earlier - this is heavily work in progress and not ready for release. Need some more work. |
@svenka3 Nice, this is a starting point. @LarsAsplund What about creating a Icarus branch under https://github.com/VUnit/vunit/ where we can work on. If the branch is stable and all features are working, you can merge the changes back to your main branch. What do you think? |
@feddischson What you should do is to follow the fork and pull request workflow explained here |
Ok, I've created the fork and branch, which can be found here: I also added a folder @svenka3 I've added you as Collaborator to my fork. Would you like to integrate your extensions? |
Sounds good. Do you want me to copy the files to that fork? I will have limited bandwidth this week for this. |
@feddischson - on:
IMHO we should rather port this vunit to pure Verilog or Icarus friendly SV than look for extra features with Icarus. Maybe you are saying the same thing? I was looking for what the setup/run() API inside VUNIT are supposed to do. Given that there is not much documentation on that (I didn't look deep enough maybe), it is a hit-and-try to port the code is what I am thinking. |
- See also VUnit#188
@svenka3 I added your files to the fork. Regarding
Both ways are possible with pros and cons.
Extension/Improvement of Icarus:
Any further pros/cons? I think we should first try to analyze the gap and then fell a decision which way we will go. |
@feddischson Anyway why not ask icarus for improvements? It is open source after all. I made tons of bug/feature issues to GHDL before it finally could run VUnit. @svenka3 |
@feddischson How is it going? |
I used the branch mentioned above for a slightly larger design with around 140 test-cases. I discovered one major thing which I need to re-write on the Python side: for each simulation, all Verilog files are compiled into one executable and then used for the simulation. This has a significant simulation speed drawback. A better approach would be just to use the test-bench files and all dependencies of a specific test, compile that and use it for the simulation. I will dig deeper into the |
Yes should be possible to compile only what is needed for each test since VUnit has the dependency graph. It has methods to get all dependencies of a node. |
When it is ready enough I want to set up Travis CI to run Verilog acceptance tests and examples using icarus. |
It may be worth adding a check for the version of iverilog, as I found out it doesn't work with versions before 10.2. I checked out the branch and had a segfault (actually in ivlpp) during the compilation step of the example. When I tried with building iverilog master to debug, everything ran fine. I checked out steveicarus/iverilog tags v10_1_1 (segfaults) and v10_2 (no segfault). The packaged version that generated the segfault was 10.1 (stable), doesn't look many distros supply a newer version. |
- See also VUnit#188
- See also VUnit#188
Maybe we can create an |
I am interested on that :-D any news? Or Verilator? |
FTR, steveicarus/iverilog#191 was implemented. According to steveicarus/iverilog#191 (comment), steveicarus/iverilog#192 is the remaining required feature for VUnit support. |
I am also interested in iverilog support. Is there a schedule for this feature ? |
@sschmitz86 First iverilog has to do there part and I'm not sure if there is a schedule for that. |
@sschmitz86 see also #925. |
If is see it correct, steveicarus/iverilog#191 is already closed. |
@umarcor well , you did already answer my question above. I did not saw that ... sorry, i will ask if there is a schedule for steveicarus/iverilog#192 |
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icarus verilog
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