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Verilog compilation failure with System Verilog flag #268

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gsorrenti opened this issue Aug 3, 2017 · 0 comments
Closed

Verilog compilation failure with System Verilog flag #268

gsorrenti opened this issue Aug 3, 2017 · 0 comments

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@gsorrenti
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In case of modelsim the vlog option "-sv" may generate false error. For example some reserved word in System Verilog is legal in Verilog generating compilation failure (in my case the problem was with a register named "TYPE").

Probably similar failure could apply to other simulators. It should be checked.
nathanaelhuffman pushed a commit to nathanaelhuffman/vunit that referenced this issue Jul 30, 2018
@kraigher @nathanaelhuffman
Add support for non-system-verilog verilog files. Closes VUnit#268
35f98de
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@gsorrenti