Parsing macro

[alinaivanovaoff]

When I use such macro directly in Modelsim simulation, I don't get any warning. When I use VUnit I get a warning.
Macro:

`define scsMsg(inf)                  $display("SUCCESS: %s!", inf);

Usage of this macro

`scsMsg({name, " CHECK DATA: output data is equal to benchmark"})

'name' is string

Warning

WARNING - Too many arguments got 2 expected 1
at ..\..\common\tb\com_tst_pkg.sv line 348:
                        `scsMsg({name, " CHECK DATA: output data is equal to benchmark"})

[alinaivanovaoff]

If I add additional var:

string full_name;
full_name = {name, " CHECK DATA: output data is equal to benchmark"};
`scsMsg(full_name)

There is no warning.
It's a bit strange.

[kraigher]

The warning is not printed by Modelsim but by VUnit. Thus you only see it when running VUnit.

VUnit has a Verilog preprocessor since it it is necessary to perform preprocessing to scan for module dependencies since module can be defined or instantiated in a macro. You have discovered a bug in the VUnit Verilog preprocessor. It has no consequence for you other than seeing the warning if the macro was not defining an item which effects compile dependencies which it seems your macro does not.

[svenka3]

Nice explanation. Will you consider adding a unique prefix to your preprocessor messages so that it is easier for users to isolate?

Thanks

[kraigher]

Sure we could add a prefix so that the user does not get confused. Note though that these warnings occur before any compilation (and output for compiling file ...) started so it could not come from the vendor tool.

[kraigher]

I made a fix for this now.

[kraigher]

Now part of 2.4.2 release.