Verilog parser won't detect an instance within generate

[feddischson]

The following is not detected correctly by verilog_parser.py:

module name;
genvar i;
  generate
    for( i=0; i < 10; i = i + 1 ) 
      begin: INST_GEN
        true1 instance_name1();
    end
  endgenerate
endmodule

It takes INST_GEN instead of true1.

A unit test to demonstrate this can be found here. I further added a pull-request for this unit-test.

[feddischson]

I haven't been able to fix this after a short view on the code.
Also multiple cascaded generate loops needs to be handled somehow.