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Do not add builtins by default #559

Closed
Tracked by #763
umarcor opened this issue Oct 7, 2019 · 2 comments · Fixed by #764
Closed
Tracked by #763

Do not add builtins by default #559

umarcor opened this issue Oct 7, 2019 · 2 comments · Fixed by #764

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@umarcor
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umarcor commented Oct 7, 2019

From #507 (comment):

[@kraigher]
This is really an old mistake that I think we made that I might want to change. It would have been better not to add the builtins by default since it makes options easier and also we do not require a separate VUnit class to be used for Verilog.

[@umarcor]
Do you mean to remove compile_builtins from from_argv and from_args? That'd be a breaking change, wouldn't it?

@kraigher
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I do not think this is urgent to do. But when we see a reason where this change would make our life easier we should do it. Currently I think we can wait.

@kraigher
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When doing this change we should replace the add_builtins method with an add_vhdl_builtins and add_verilog_builtins method.

umarcor added a commit to dbhi/vunit that referenced this issue Oct 21, 2021
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@eine eine added this to the v5.0.0 milestone Oct 21, 2021
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@eine eine modified the milestones: v5.0.0, v5x Apr 19, 2023
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@eine eine modified the milestones: v5.1.0, v5.0.0 Apr 23, 2023
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@eine eine closed this as completed in #764 Apr 23, 2023
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