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vcomponents tests are failling with ModelSim #642
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@NanooooK is this still failing with v4.5.0 or v4.6.0? |
I also have fails using:
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle (3.9 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle (4.1 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle (3.5 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle (3.6 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle (3.3 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle (3.1 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle (3.0 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle (3.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=0.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=8.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=0.test back-to-back failing check (2.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=8.test back-to-back failing check (2.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=0.test back-to-back failing check (2.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=8.test back-to-back failing check (2.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=0.test back-to-back failing check (2.3 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=8.test back-to-back failing check (2.3 seconds)
=================================================================================================================================================================================
pass 484 of 500
fail 16 of 500
=================================================================================================================================================================================
Total time was 1288.9 seconds
Elapsed time was 1290.6 seconds
=================================================================================================================================================================================
Some failed! Tell me if you need more inputs. |
I also have fails using:
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle (2.6 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle (2.7 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle (2.8 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle (2.6 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle (2.6 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle (2.7 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle (2.7 seconds)
fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle (2.5 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=0.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=8.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=0.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=8.test back-to-back failing check (2.5 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=0.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=8.test back-to-back failing check (2.5 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=0.test back-to-back failing check (2.4 seconds)
fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=8.test back-to-back failing check (2.4 seconds)
=================================================================================================================================================================================
pass 484 of 500
fail 16 of 500
=================================================================================================================================================================================
Total time was 1308.8 seconds
Elapsed time was 1310.4 seconds
=================================================================================================================================================================================
Some failed! |
I didn't manage to recreate this problem in GHDL when using $ ghdl --version
GHDL 2.0.0-dev (1.0.0.r89.g7722e309) [Dunoon edition]
Compiled with GNAT Version: 10.2.0
mcode code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2021 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ python --version
Python 3.9.5 It was reproduceable in ModelSim and I fixed the root problem (delta cycle race conditions). Please verify in your GHDL setup. |
I launched a new test by setting |
Yes, that is weird. The commit only changes VHDL files so I can't see that I introduced anything that will cause that. It happens to me sometimes but that is usually because I misspell, for example Anyway, I noticed that my fix isn't good enough. It now fails with GHDL for me locally while ModelSim that used to fail works. At least for |
I tested that on the 4.6.0. I will retry later after re-installing ghdl properly (this should have nothing to do with your commit). |
I think I fixed it now. https://github.com/VUnit/vunit/actions/runs/2179374584 looks better but has yet to complete. |
I merged the fix to master so you should be able to test it from there. |
I have tested, with modelsim, everything pass. |
Test done using the container GHDL 3.0.0-dev (v2.0.0-93-gff5c35e4) [Dunoon edition]
Compiled with GNAT Version: 9.3.0
GCC back-end code generator With VUnit: issue a0e25830ad28f9ed2009c3e2da426cae3be2e40 Results: ==================================================
pass 500 of 500
==================================================
Total time was 2552.1 seconds
Elapsed time was 2555.5 seconds
==================================================
All passed! |
Great, in that case we can close this issue. |
When running vcomponents tests, several are failling:
tox -v -e py36-vcomponents-modelsim
Details for the failures can be found here and there.
Environment is VUnit 4.4.0 and ModelSim 10.6c.
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