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Working Xcelium + Indago support with single command commpilation plus a basic rerun script for Xcelium #866

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2 changes: 1 addition & 1 deletion tests/acceptance/test_artificial.py
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ class TestVunitArtificial(unittest.TestCase):
"""

def setUp(self):
if simulator_is("activehdl"):
if simulator_is("activehdl", "incisive", "xcelium"):
self.output_path = str(ROOT / "artificial_out")
else:
# Spaces in path intentional to verify that it is supported
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1,150 changes: 1,150 additions & 0 deletions tests/unit/test_xcelium_interface.py

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60 changes: 60 additions & 0 deletions tools/xcelium_verilog_fixup.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
# This Source Code Form is subject to the terms of the Mozilla Public
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This file should be removed as it is no longer necessary.

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Is it needed for older versions of Xcelium?

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No. It was added by @rodrigomelo9 in their original PR and was made irrelevant by our inclusion of the patches to the files in this PR.

# License, v. 2.0. If a copy of the MPL was not distributed with this file,
# You can obtain one at http://mozilla.org/MPL/2.0/.
#
# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com

"""
Perform necessary modifications to VUnit Verilog code to support
Cadence Xcelium
"""

import os
import re
from pathlib import Path


def replace_stop_by_finish(file_name):
"""
Replace $stop by $finish
"""

with Path(file_name).open("r", encoding="iso-8859-1") as fptr:
text = fptr.read()

text = text.replace("$stop(", "$finish(")

with Path(file_name).open("w", encoding="iso-8859-1") as fptr:
fptr.write(text)


def add_finish_after_error(file_name):
"""
Add $finish after a $error
"""

with Path(file_name).open("r", encoding="iso-8859-1") as fptr:
text = fptr.read()

text = re.sub(r"(\$error\(.*\))", "\\1; $finish(1)", text)

with Path(file_name).open("w", encoding="iso-8859-1") as fptr:
fptr.write(text)


def main():
"""
Remove xcelium incompatabilities from source code
"""
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where = "../vunit/verilog"
root = os.path.abspath(os.path.join(os.path.dirname(__file__), where))
for base, _, files in os.walk(root):
for file_name in files:
if file_name.endswith(".sv") or file_name.endswith(".svh"):
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replace_stop_by_finish(os.path.join(base, file_name))
add_finish_after_error(os.path.join(base, file_name))


if __name__ == "__main__":
#main()
print("nothing to do")
3 changes: 2 additions & 1 deletion vunit/configuration.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
import inspect
from pathlib import Path
from copy import copy
from vunit.sim_if.factory import SIMULATOR_FACTORY



LOGGER = logging.getLogger(__name__)
Expand Down Expand Up @@ -123,6 +123,7 @@ def set_sim_option(self, name, value):
"""
Set sim option
"""
from vunit.sim_if.factory import SIMULATOR_FACTORY
SIMULATOR_FACTORY.check_sim_option(name, value)
self.sim_options[name] = copy(value)

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3 changes: 2 additions & 1 deletion vunit/project.py
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@
)
from vunit.vhdl_standard import VHDL, VHDLStandard
from vunit.library import Library
from typing import List

LOGGER = logging.getLogger(__name__)

Expand Down Expand Up @@ -430,7 +431,7 @@ def _get_compile_timestamps(self, files):
timestamps[source_file] = ostools.get_modification_time(hash_file_name)
return timestamps

def get_files_in_compile_order(self, incremental=True, dependency_graph=None, files=None):
def get_files_in_compile_order(self, incremental=True, dependency_graph=None, files=None) -> List[SourceFile]:
"""
Get a list of all files in compile order
param: incremental: Only return files that need recompile if True
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4 changes: 3 additions & 1 deletion vunit/sim_if/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,8 @@ class SimulatorInterface(object): # pylint: disable=too-many-public-methods
# True if simulator supports ANSI colors in GUI mode
supports_colors_in_gui = False

incremental_compile = True

def __init__(self, output_path, gui):
self._output_path = output_path
self._gui = gui
Expand Down Expand Up @@ -259,7 +261,7 @@ def compile_source_files(
failures = []

if target_files is None:
source_files = project.get_files_in_compile_order(dependency_graph=dependency_graph)
source_files = project.get_files_in_compile_order(incremental=self.incremental_compile, dependency_graph=dependency_graph)
else:
source_files = project.get_minimal_file_set_in_compile_order(target_files)

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4 changes: 2 additions & 2 deletions vunit/sim_if/cds_file.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
# Copyright (c) 2014-2022, Lars Asplund lars.anders.asplund@gmail.com

"""
Handles Cadence Incisive .cds files
Handles Cadence Incisive/Xcelium .cds files
"""

import re
Expand All @@ -14,7 +14,7 @@

class CDSFile(dict):
"""
Handles Cadence Incisive .cds files
Handles Cadence Incisive/Xcelium .cds files

Only cares about 'define' but other lines are kept intact
"""
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2 changes: 2 additions & 0 deletions vunit/sim_if/factory.py
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
import os
from .activehdl import ActiveHDLInterface
from .ghdl import GHDLInterface
from .xcelium import XceliumInterface
from .incisive import IncisiveInterface
from .modelsim import ModelSimInterface
from .rivierapro import RivieraProInterface
Expand All @@ -32,6 +33,7 @@ def supported_simulators():
RivieraProInterface,
ActiveHDLInterface,
GHDLInterface,
XceliumInterface,
IncisiveInterface,
]

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21 changes: 3 additions & 18 deletions vunit/sim_if/incisive.py
Original file line number Diff line number Diff line change
Expand Up @@ -38,22 +38,7 @@ class IncisiveInterface(SimulatorInterface): # pylint: disable=too-many-instanc

sim_options = [ListOfStringOption("incisive.irun_sim_flags")]

@staticmethod
def add_arguments(parser):
"""
Add command line arguments
"""
group = parser.add_argument_group("Incisive irun", description="Incisive irun-specific flags")
group.add_argument(
"--cdslib",
default=None,
help="The cds.lib file to use. If not given, VUnit maintains its own cds.lib file.",
)
group.add_argument(
"--hdlvar",
default=None,
help="The hdl.var file to use. If not given, VUnit does not use a hdl.var file.",
)
# NOTE: Incisive shares the command-line arguments with Xcelium
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This comment relates to the code that was removed, this should be in a commit message instead. I personally don't think this comment is needed, but I would clean it up to include add_argument is excluded because X

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IMO we could even remove all traces of Incisive, its last release was in 2015, everything after that was called Xcelium.

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Would the Incisive from 2015 work with the new Xcelium interface?

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I honestly don't know. Our codebase is incompatible with Incisive due to reliance on newer System Verilog features.


@classmethod
def from_args(cls, args, output_path, **kwargs):
Expand Down Expand Up @@ -102,14 +87,14 @@ def find_cds_root_irun(self):
"""
Finds irun cds root
"""
return subprocess.check_output([str(Path(self._prefix) / "cds_root"), "irun"]).splitlines()[0]
return subprocess.check_output([str(Path(self._prefix) / "cds_root"), "irun"]).splitlines()[0].decode()

def find_cds_root_virtuoso(self):
"""
Finds virtuoso cds root
"""
try:
return subprocess.check_output([str(Path(self._prefix) / "cds_root"), "virtuoso"]).splitlines()[0]
return subprocess.check_output([str(Path(self._prefix) / "cds_root"), "virtuoso"]).splitlines()[0].decode()
except subprocess.CalledProcessError:
return None

Expand Down