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week1: DATA WIDTH- 8 inputs with 8 bit data width
Description: In the first stage of the adder tree, consist of four two input adders ( 8 bit inputs) and provides output of 9 bits (carry). These four outputs are the inputs for stage 2 of the adder tree, where we use two adders (9bit input) to provide outputs of 10bits(carry) and finally this is summed in a 10 bit adder to provide a 11 bit output. This design is the basis for DSP applications.
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week2: DATA WIDTH- 8 inputs with 8 bit data width
Description: Insert pipeline stages in the previous full width adder tree design in the regions indicated by the dotted lines. The data from the previous stage enters the next only at the positive edge of the clock, when enable signal is high. The data also resets to zero if the reset signal is pulled high.
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week3:
Description: For the Pipelined Adder tree design, include a new approximator block AXA for the last 3 bits of the input’s LSB to design two different tree designs, each performing (i) bitwise or operation in AXA block (ii) bitwise xor operations in AXA block as depicted in the diagram below.
For example, given two inputs X and Y in the adder tree, The AXA block for bitwise or is depicted in red as follows, while normal addition operation is performed in the blue box.
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week4:
Perform Approximation D1 and D2 for the Pipelined Adder tree design
