Design: 8-bit Vedic Multiplier

About the repository

Welcome to my GitHub repository dedicated to VLSI ASIC Design for ASICs using open-source tools! Here, we embark on a journey that starts with specifications and build the Design from scratch, taking them through the entire RTL to GDS process that meets various Performance, Power, Area ( PPA ) and manufacturability requirements. The best part? We're doing it all with open-source tools.

8-bit Vedic Multiplier

Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has led to the emergence of Vedic Multipliers as one of the fastest and low power multipliers over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed.

8-bit Vedic Multiplier

RTL simulation :

iverilog  vedic8x8.v vedic4x4.v vedic2x2.v ripple_adder_12bit.v ripple_adder_8bit.v ripple_adder_6bit.v ripple_adder_4bit.v full_adder.v half_adder.v test.v -o vedic.out

RTL Synthesis :

read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

read_verilog vedic8x8.v vedic4x4.v vedic2x2.v ripple_adder_12bit.v ripple_adder_8bit.v ripple_adder_6bit.v ripple_adder_4bit.v full_adder.v half_adder.v

synth -top vedic8x8

abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

flatten

show
write_verilog -noattr pes_vedic.v

GLS Simulation:

 iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v pes_vedic.v test_copy.v -o vedic_rtl.out

Physical design using OpenLane

Follow the instructions for the installation of Openlane using the original Documentation.OpenLane Installation

All the design variables needed for the physical design are mentioned in this documentation Flow Configuration Variables. Most of the issues and errors at any time/stage during the flow can be fixed by looking at the erros.log and corresponding log files. Additionally, having an overall understanding of the global necessary variable is crucial.

Create a design folder in Openlane

To create a design folder with a default config.json file, use command :

cd
cd OpenLane
make mount
./flow.tcl -design <DESIGN_NAME> -init_design_config

Adding your verilog file

A new directory "openlane" will be created where your design will be housed.

In a new tab, [don't unmount the Openlane process], use these to source your design verilog files.

cd ~/OpenLane/openlane/<YOUR_DESIGN>
mkdir src
cd src

moves all your Verilog codes in this src directory.

Add the path to the Verilog files in the field VERILOG_FILES in the default config.json

dir::src/pes_vedic_mul.v

Looking the Flow variables and through prior knowledge, I have inserted a few parameters that the tool can use during different stages

with we are ready to experiment with our design variables.

OpenLane Automated flow

• With the design variables, run an automated flow to check for any errors. After each run check the log files and fix the errors by adjusting or adding the design parameter in the config.json file
• Looking out for warnings, this will help us to declare a few more design parameters

to run automated flow use the command in the openlane make mount session:

./flow.tcl -design openlane/pes_vedic_mul -tag run_1

• After 3 unsuccessful runs and fixing the error at each run, I was finally successful on the 4th run.

Results:

Synthesis :

all the designs are meeting setup and hold requirements

Floorplan:

Placements:

CTS:

Routing:

Final GDS file :

klayout -e -nn $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyt    -l $PDK_ROOT/sky130A/libs.tech/klayout/tech/sky130A.lyp    ./openlane/pes_vedic_mul/runs/run_4/results/final/gds/pes_vedic_mul.gds