Bug fixes

basic_and.py

@@ -0,0 +1,19 @@
+from pywire import *
+
+
+def invert(signal):
+    if signal:
+        return False
+    else:
+        return True
+
+
+class Inverter:
+    def __init__(self, a, b):
+        b.drive(invert, a)
+
+width = 4
+a = Signal(width, io="in")
+b = Signal(width, io="out")
+Inverter(a, b)
+build()

bram_test.py

@@ -0,0 +1,3 @@
+from pywire import *
+
+a_write_en

camera_example.py

@@ -0,0 +1,70 @@
+from pywire import *
+
+camera_clock = Signal(1, io="out", port="P40")  # 25MHz
+
+
+def halve_frequency(slow_clock):
+    return not slow_clock
+
+
+# MojoV3 clock is 50MHz, camera_clock is 25 MHz.
+camera_clock.drive(halve_frequency, camera_clock)
+
+
+# Timing signals incoming from camera
+frame_invalid = Signal(1, io="in", port="P26")  # New frame trigger coming from camera. Aka VSYNC
+line_valid = Signal(1, io="in", port="P34")  # New line trigger coming from camera. AKA HREF
+pixel_clock = Signal(1, io="in", port="P23")  # New pixel trigger coming from camera. AKA PCLK
+
+
+def _(x):
+    return x
+
+
+def invert(x):
+    return not x
+
+
+# pixel_clock (1 cycle down), line_valid (1 cycle down) and frame_valid (no clock)
+pixel_clock_1d = Signal(1)
+pixel_clock_1d.drive(_, pixel_clock)
+line_valid_1d = Signal(1)
+line_valid_1d.drive(_, line_valid)
+frame_valid = Signal(1)
+frame_valid.drive(invert, frame_invalid, clock=False)
+
+"""
+camera_x = Signal(10)  # Derived from pixel_clock, pixel_clock_1d, line_valid
+camera_y = Signal(10)  # Derived from pixel_clock, pixel_clock_1d, line_valid, line_valid_1d, frame_invalid
+
+
+def increment_on_rising(current_value, driving_signal, driving_signal_1d, clear):
+    if clear:
+        return 0
+    elif driving_signal and not driving_signal_1d:
+        return current_value + 1
+
+
+camera_x.drive(increment_on_rising, (camera_x, pixel_clock, pixel_clock_1d, line_valid))
+camera_y.drive(increment_on_rising, (camera_y, line_valid, line_valid_1d, frame_invalid))
+
+# 8 bit RGB data coming from the camera
+new_data = Signal(8, io="in", port=['P9', 'P11', 'P7', 'P14', 'P5', 'P16', 'P2', 'P21'])
+get_camera_x = Signal(10, io="in")
+get_camera_y = Signal(10, io="in")
+response = Signal(8, io="out", port=["P134", "P133", "P132", "P131", "P127", "P126", "P124", "P123"])
+
+
+def update_response(camera_data, camera_x, camera_y, get_camera_x, get_camera_y):
+    if camera_x == get_camera_x and camera_y == get_camera_y:
+        return camera_data
+
+
+response.drive(update_response, (new_data, camera_x, camera_y, get_camera_x, get_camera_y))
+
+
+"""
+rename_signals(globals())
+build()
+#launch_test()
+#print(generate(name="blink_example"))

examples/blink_example2.py

@@ -10,8 +10,7 @@ def logic(counter, led):
 	else:
 		led1 = 0
 
-
-build(logic, (counter, led1))
+led1.drive(logic, counter)
 
 print(vhdl(globals(), name="blink_example"))
 print(timing(globals(), 50, 'P56', vendor="Xilinx"))

examples/bram_example.py

@@ -6,10 +6,15 @@
 bram_write_en = Signal(1, io="in", port="P41")
 bram_read = Signal(8, io="out", port=["P134", "P133", "P132", "P131", "P127", "P126", "P124", "P123"])
 
-mem.a_address.drive(bram_address)
-mem.a_data_in.drive(bram_write_data)
-mem.a_write_en.drive(bram_write_en)
-bram_read.drive(mem.a_data_out)
+def identity(x):
+    return x
 
-print(vhdl(globals(), name="bram_example"))
-print(timing(globals(), 50, 'P56', vendor="Xilinx"))
+
+mem.a_address.drive(identity, bram_address)
+mem.a_data_in.drive(identity, bram_write_data)
+mem.a_write_en.drive(identity, bram_write_en)
+bram_read.drive(identity, mem.a_data_out)
+
+rename_signals(globals())
+print(generate(name="bram_example"))
+#print(timing(globals(), 50, 'P56', vendor="Xilinx"))

examples/camera_example.py

@@ -1,9 +1,13 @@
 from pywire import *
 
 camera_clock = Signal(1, io="out", port="P40")  # 25MHz
-frame_invalid = Signal(1, io="in", port="P26")  # New frame trigger coming from camera. Aka VSYNC
+
+frame_done = Signal(1, io="in", port="P26")  # New frame trigger coming from camera. Aka VSYNC
 line_valid = Signal(1, io="in", port="P34")  # New line trigger coming from camera. AKA HREF
 pixel_clock = Signal(1, io="in", port="P23")  # New pixel trigger coming from camera. AKA PCLK
+pixel_clock_1d = Signal(1)
+
+pixel_clock_1d.drive(_, pixel_clock, clock=True)
 
 # 8 bit RGB data coming from the camera
 new_data = Signal(8, io="in", port=['P9', 'P11', 'P7', 'P14', 'P5', 'P16', 'P2', 'P21'])
@@ -17,10 +21,7 @@
 
 
 def halve_frequency(slow_clock):
-	if slow_clock == 1:
-		return 0
-	else:
-		return 1
+	return not slow_clock
 
 
 camera_clock.drive(halve_frequency, args=camera_clock)

examples/component_example.py

@@ -7,7 +7,7 @@
 
 entity inverter is
     port(
-    clock : in std_logic;
+    clock : in std_logic_vector(0 to 0);
     a : in std_logic_vector(0 to 0);
     b : out std_logic_vector(0 to 0));
 end entity;
@@ -24,8 +24,7 @@
 a_out = Signal(1, name="a_outer", io="in", port=["P1"])
 b_out = Signal(1, name="b_outer", io="out", port=["P2"])
 
-inverter = FromText(component_text)
-inverter.link({"a": a_out, "b": b_out})
+inverter = FromText(component_text, {"a": a_out, "b": b_out})
 
 print(vhdl(globals(), name="component_example"))
 print(timing(globals(), 50, 'P56', vendor="Xilinx"))

iCloud

@@ -0,0 +1 @@
+/Users/2017-A/Library/Mobile Documents

inverter_test.py

@@ -0,0 +1,38 @@
+from pywire import *
+
+class Inverter(Component):
+    count = 0
+
+    @staticmethod
+    def identity(x):
+        return x
+
+    def __init__(self, size, signal_in, signal_out):
+        Component.__init__(self)
+        Inverter.count += 1
+        self.id = Inverter.count
+        self.size = size
+        self.signal_in = signal_in
+        self.signal_out = signal_out
+
+    def header(self):
+        return """
+            component inverter is
+                generic (N: positive);
+                port(
+                    clock : in std_logic_vector(0 to 0);
+                    a, b  : in_std_logic_vector(0 to N-1));
+            end component;
+        """
+
+    def body(self):
+        return "INVERTER_" + str(self.id) + " : inverter \n" +\
+            "generic map (N => " + str(self.size) + ")\n port map (" +\
+                self.signal_in.name + ", " + self.signal_out.name + ")\n"
+
+
+width = 4
+a = Signal(width, io="in")
+b = Signal(width, io="out")
+Inverter(width, a, b)
+print(generate())

pywire/README.md

@@ -0,0 +1,3 @@
+# DESIGN DOC
+
+## 

pywire/__init__.py

@@ -1,4 +1,5 @@
-from .main import Signal, vhdl, timing
-from .bram import BRAM
-from .component import Component, FromText
+from .component import Component, FromText, BRAM
+from .signal import Signal
+from .ast_logic import *
+from .test_suite import launch_test
 from .build import build