Switchs order of output ports #1006
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Other solution is to always sort from left to right in ascending order of sort_keys and lose compatibility. |
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Decision after today's meeting: change sort_keys as well so they everything is in a consistent order, from left to write. Break compatibility, fix packages that need fixing. |
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Made the change. Also updated the test files. |
This orders ports by increasing sort_key then id, and draws both input and output ports from left to right. Modules on which sort_keys had been set (backwards) specifically to have the ports in the right order will need to be updated.
remram44
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Mar 16, 2015
Switchs order of output ports
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Thanks for the sklearn fixes :) |
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This draws output ports from left to right, ordering them in descending order of sort_keys when provided. Input port are still sorted by ascending order of sort_keys. This should keep the order of output ports if the package author bothered to provide sort_keys, else it will change the order to match the declaration order. Hence it is surprising.
My test case is this: https://gist.github.com/remram44/f1a459fd3452cbc120d1
Highlighted connections are between port specs, not module ports.
master:
There is something strange going on in the ordering of port specs with the same sort_key. I didn't bother keeping compatibility there.
This PR:
Note that sort keys are backwards for both FixedOrder#_output_ports, and the sort_keys in ports.xml. This is for compatibility reasons.
This means that a PythonSource's output ports are still drawn from right to left, because sort_keys are assigned to them, in ascending order.
Fixes #980