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Chapter 3 - CORDIC

Comparation between HLS code and Chisel code.

Environment

  • Vitis HLS 2021.1
  • Vivado 2021.1
  • Xilinx xc7a200tfbg676-2

Architecture

  • 16 pipeline stages
  • 16-bit fixed point with 15 binary points

Quantization

  • Angle:
  • Cosine & Sine:

Utilization

LUT FF BRAM DSP
HLS CORDIC Baseline 421 107 0 0
Chisel CORDIC 686 639 0 0

Performance

Latency(ns) Period(ns) Interval
HLS CORDIC Baseline 500 51 49
Chisel CORDIC 160 10 1

Accuracy

Cosine total error Sine total error
HLS CORDIC Baseline 157.947048 91.995215
Chisel CORDIC 0.071231 0.023446