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dwmac: sync clock and reset drivers
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Change-Id: I0283618f4c978e9348db58e7687fe8909c4a533a
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X547 committed Jun 14, 2023
1 parent 7c7eb04 commit b30cfb7
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Showing 3 changed files with 6 additions and 10 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -44,13 +44,8 @@ status_t StarfiveClock::SetEnabled(uint32 id, bool doEnable)
if (!GetRegs(id, regs))
return ENOENT;

StarfiveClockRegs regsVal {.val = regs->val};
dprintf("clk-gate: readl(%16" B_PRIx64 ") -> %#" B_PRIx32 "\n", (addr_t)regs, regsVal.val);
regsVal.enable = doEnable;
regs->val = regsVal.val;
dprintf("clk-gate: writel(%#" B_PRIx32 ", %16" B_PRIx64 ") -> \n", regsVal.val, (addr_t)regs);
regs->enable = doEnable;

// regs->enable = doEnable;
return B_OK;
}

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Original file line number Diff line number Diff line change
Expand Up @@ -37,5 +37,8 @@ class StarfiveClock {
status_t SetEnabled(uint32 id, bool doEnable);

uint64 GetRate(uint32 id);
status_t SetRate(uint32 id, uint64 rate);
status_t SetRate(uint32 id, uint64 rate /* Hz */);

uint32 GetParent(uint32 id);
status_t SetParent(uint32 id, uint32 parentId);
};
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ bool StarfiveReset::IsAsserted(uint32 id)
uint32 mask = 1 << (id % 32);
uint32 value = *assertAndStatus.status;

return (value & mask) != 0;
return (value & mask) == 0;
}

status_t StarfiveReset::SetAsserted(uint32 id, bool doAssert)
Expand All @@ -75,7 +75,6 @@ status_t StarfiveReset::SetAsserted(uint32 id, bool doAssert)
uint32 done = 0;

uint32 value = *assertAndStatus.assert;
dprintf("reset: readl(%16" B_PRIx64 ") -> %#" B_PRIx32 "\n", (addr_t)assertAndStatus.assert, value);
if (doAssert) {
value |= mask;
} else {
Expand All @@ -84,7 +83,6 @@ status_t StarfiveReset::SetAsserted(uint32 id, bool doAssert)
}

*assertAndStatus.assert = value;
dprintf("reset: writel(%#" B_PRIx32 ", %16" B_PRIx64 ")\n", value, (addr_t)assertAndStatus.assert);

uint32 attempts = 10000;
do {
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