The main purpose of this repository is to provide PL test harness that help AIE application designers to do quick build and on-board tests with VCK190.
Vitis allows compiling an AIE graph using a precompiled .xsa as an input platform to skip v++ link stage and directly go to v++ package stage. This will save the most time consuming part of compiling and generate the final .xclbin file for on-board tests.
The test harness consists of three parts:
- An HLS based test harness design on PL. It can feed data to AIE application or fetch data from AIE application via AXI-stream.
- An ADF dummy graph design on AIE. If user AIE application did not utilize all PLIOs provided by test harness, it would occupy the unused PLIOs to help pass v++ package stage.
- A suite of software APIs on host side to help initialize device and run tests.
Test harness on PL consist of 72 channels, 36 of them feed data to AIE and the rest 36 fetch data from AIE. Each channel contains its own URAM buffer which is 128bits x 4096 and its own AXI-stream port for input or output.
The input channel works in steps below:
- All input channels will load input data for AIE from DDR and store them in URAM buffer.
- After all data has been stored in URAM buffer, each channel will start to do its own count down. This allows input channels start to send data to AIE at different cycles.
- Each channel load from URAM buffer and send desired amount of data to AIE. Each of them can repeat the sending with specified rounds.
- Each channel can record the latency between the cycle in which it starts to send data to AIE and the cycle in which it finishes all sendings.
The output channels works in steps described as below:
- Each channel will start to do its own count down. This allows output channels start to fetch data from AIE at different cycles.
- Each channel fetch desired amout of data from AIE and store them in URAM buffer. Each of them can repeat the fetching with specified rounds.
- After all output channels finished all fetchings, they will write output data on URAM to DDR.
- Each channel can record the latency between the cycle in which it starts to fetch data from AIE and the cycle in which it finishes all fetchings.
The data sizes to feed to/fetch from AIE, count-down cycles and repetition number of each channel are all set by config buffer on DDR which is set by software API. The latency cycles of each channels will be stored to DDR and fetch back and displayed by software API.
Test harness on PL provides 36 PLIO for input and 36 PLIO for output. If user graph does not utilize all of them, it will lead to package error. Dummy graph can be used to occupy all dangling PLIOs. The dummy graph won't do anything but help packaging. To help dummy graph identify all dangling PLIOs, user graph needs to register all used PLIOs. For details, please take reference from "Step by Step Example" section in the documentation.
We provide software APIs to make 3-steps on board run:
- Initialize device and load xclbin.
- Set data which will be fed to AIE and data which will be fetch from AIE.
- Run user graph.
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