This HPC repository provides solutions and POCs for accelerating applications in heterogeneous HPC systems, especially FPGA-enabled HPC system. The focus of this repository is to provide ready-to-use products that can benefit from the performance, power and cost improvement offered by FPGA-enabled HPC systems. Those system setups can be a single CPU server with multiple FPGA accelerator cards, a multiple of those servers or even a multiple HPC servers with different accelerator cards, e.g. GPU and FPGA cards. The pure FPGA-related accelerator implementation can be found in L1 and L2 directories. Just like the file organization of Vitis_libraries, the L1 directory contains the basic hardware routines intented to be used in bigger hardware accelerator implementation. The L2 directory contains the standalone FPGA accelerator implementation. That is, those accelerators or CUs (compute units) can be addressed or used to interact with CPU code / software via XRT functions calls. The application level solutions that can be deployed on multiple FPGA cards and multiple HPC servers can be found directly under the root directory of the repository. Currently, we provide a product called xJPCG, which is a conjugate gradient solver with Jacobi preconditioner. More detailed documentation is availabe at Xilinx HPC Products Github Pages
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Copyright 2021-2022 Xilinx, Inc.
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Copyright 2021-2022 Xilinx, Inc.