Clarify for single interrupt designs

docs/source/overlay_design_methodology/pspl_interface.rst

@@ -103,10 +103,12 @@ interrupts must be attached to an **AXI Interrupt Controller** which is in turn
 attached to the first interrupt line to the processing system. If more than 32
 interrupts are required then AXI interrupt controllers can be cascaded. This
 arrangement leaves the other interrupts free for IP not controlled by PYNQ
-directly such as SDSoC accelerators.
+directly such as Vitis accelerators. The AXI Interrupt Controller can be avoided
+for overlays with only one interrupt, in such overlays the interrupt pin must be
+connected to the first interrupt line of the processing system.
 
 Interrupts are managed by the Interrupt class, and the implementation is built
-on top of *asyncio*, part of the Python standard library. 
+on top of *asyncio*, part of the Python standard library.
 
 
 More information about using the Interrupt class can be found in the 

docs/source/pynq_libraries/interrupt.rst

@@ -35,12 +35,9 @@ To integrate into the PYNQ framework Dedicated interrupts must be attached to an
 `AXI Interrupt Controller <https://www.xilinx.com/products/intellectual-property/axi_intc.html#documentation>`_
 which is in turn attached to the first interrupt line to the processing system.
 
-If interrupts are directly connected to the PS, PYNQ will report a warning
-and ignore the interrupt. For instance,
-
-   .. code-block:: Python
-
-      RuntimeWarning: axi_iic_0 interrupt is ignored because there is no associated AXI Interrupt controller
+The AXI Interrupt Controller can be avoided for overlays with only one
+interrupt, in such overlays the interrupt pin must be connected to the
+first interrupt line of the processing system.
 
 PYNQ only support interrupts that are ultimately connected to IRQ_F2P[0].