Traverse Axis Clock Converter. RapidWright integration

Xilinx · Feb 1, 2022 · a688f46 · a688f46
1 parent fa1b66c
commit a688f46
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/pynq_composable/parser.py b/pynq_composable/parser.py
@@ -18,7 +18,8 @@
 _m_type = ['MASTER', 'INITIATOR']
 _s_type = ['SLAVE', 'TARGET']
 _mem_items = ['axis_register_slice', 'axis_data_fifo', 'fifo_generator',
-              'axis_dwidth_converter', 'axis_subset_converter']
+              'axis_dwidth_converter', 'axis_subset_converter',
+              'axis_clock_converter']
 
 _dfx_item = ['dfx_decoupler']
 _axis_vlnv = 'xilinx.com:interface:axis:1.0'