Update partial bitstream documentation

Xilinx · Nov 17, 2021 · b84298e · b84298e
1 parent e574c0b
commit b84298e
Showing 1 changed file with 10 additions and 9 deletions.
diff --git a/pynq_composable/composable.py b/pynq_composable/composable.py
@@ -144,21 +144,22 @@ def __init__(self, description):
         to be next to bitstream file that was used to create the Overlay object
         The name convention for partial bitstreams and HWH file is
 
-        <bitstream_name>_<pr_region>_<pr_module_name>.{bit|hwh}
+        <bitstream_name>_<hierarchy>_<pr_region>_<pr_module_name>.{bit|hwh}
 
         For instance if the main bitstream is `base.bit` and there are two DFX
         regions with the names `pr_0` and `pr_1` each of them with the same
         two reconfigurable module, `function_1` and `function_2` the names
         should be as follow
 
-            base_pr_0_function_1.bit
-            base_pr_0_function_1.hwh
-            base_pr_0_function_2.bit
-            base_pr_0_function_2.hwh
-            base_pr_1_function_1.bit
-            base_pr_1_function_1.hwh
-            base_pr_1_function_2.bit
-            base_pr_1_function_2.hwh
+            base_composable_pr_0_function_1.bit
+            base_composable_pr_0_function_1.hwh
+            base_composable_pr_0_function_2.bit
+            base_composable_pr_0_function_2.hwh
+            base_composable_pr_1_function_1.bit
+            base_composable_pr_1_function_1.hwh
+            base_composable_pr_1_function_2.bit
+            base_composable_pr_1_function_2.hwh
+
         """
 
         super().__init__(description)