sw_apps: zynqmp_pmufw: Implement HW exception handler for PMU

PMU is using Microblaze default HW exception handler. This patch replaces this handler with new handler which triggers FW error 1 and updates PMU peristent global storage register 5 to let user know the reason for FW error 1. PMU persistent global register 5: Bit 0 indicates IPI CRC error has occurred Bit 1 indicates HW exception has occurred Signed-off-by: Mounika Akula <mounika.akula@xilinx.com> Acked-for-series: Rajan Vaja <rajan.vaja@xilinx.com>
Xilinx · Jan 24, 2020 · b2bc5ed · b2bc5ed
1 parent 970057c
commit b2bc5ed
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Showing 4 changed files with 28 additions and 7 deletions.
diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 - 2019 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -408,3 +408,17 @@ XStatus XPfw_CoreSetIpiHandler(const XPfw_Module_t *ModPtr, XPfwModIpiHandler_t
 
 	return Status;
 }
+
+void XPfw_Exception_Handler(void)
+{
+	XPfw_Printf(DEBUG_PRINT_ALWAYS,"%s: Error! Exception has occurred\r\n",
+				__func__);
+	/* Write error occurrence to PERS register and trigger FW Error1 */
+	XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, HW_EXCEPTION_RECEIVED,
+			HW_EXCEPTION_RECEIVED);
+	XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
+			PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
+	XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
+			0x0U);
+	while(1);
+}
diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_default.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_default.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 - 2019 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -100,6 +100,9 @@ extern "C" {
 
 #define FSBL_COMPLETION			1U
 
+#define IPI_CRC_ERROR_OCCURRED	0x1U
+#define HW_EXCEPTION_RECEIVED	0x2U
+
 /* Handler Table Structure */
 typedef void (*VoidFunction_t)(void);
 struct HandlerTable{

diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_ipi_manager.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_ipi_manager.c
@@ -1,5 +1,5 @@
 /******************************************************************************
-* Copyright (C) 2015 - 2019 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -184,7 +184,9 @@ s32 XPfw_IpiReadMessage(u32 SrcCpuMask, u32 *MsgPtr, u32 MsgLen)
 	 * This is only for safety applications.
 	 */
 	if (MsgPtr[7] != XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE)) {
-		/* Trigger FW Error1 */
+		/* Write error occurrence to PERS register and trigger FW Error1 */
+		XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, IPI_CRC_ERROR_OCCURRED,
+					IPI_CRC_ERROR_OCCURRED);
 		XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
 					PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
 		XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
@@ -246,7 +248,9 @@ s32 XPfw_IpiReadResponse(const XPfw_Module_t *ModPtr, u32 SrcCpuMask, u32 *MsgPt
 	 * This is only for safety applications.
 	 */
 	if (MsgPtr[7] != XPfw_CalculateCRC((u32)MsgPtr, XPFW_IPI_W0_TO_W6_SIZE)) {
-		/* Trigger FW Error1 */
+		/* Write error occurrence to PERS register and trigger FW Error1 */
+		XPfw_RMW32(PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5, IPI_CRC_ERROR_OCCURRED,
+					IPI_CRC_ERROR_OCCURRED);
 		XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,
 					PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK);
 		XPfw_RMW32(PMU_LOCAL_PMU_SERV_ERR, PMU_LOCAL_PMU_SERV_ERR_FWERR1_MASK,

diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S b/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2020 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -41,7 +41,7 @@ _vector_interrupt:
 		.section .vectors.hw_exception, "ax"
 		.align 2
 _vector_hw_exception:
-		brai	_hw_exception_handler
+		brai	XPfw_Exception_Handler
 
 /* FW StartUP Begins Here: Initialization of the Stack and Stack Protection. */
 		.section .text