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v_sdirxss: Add SDI Rx subsystem example application
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Add the application to support the SDI Rx only example design

Signed-off-by: prasad gutti <prasadg@xilinx.com>
Acked-by: Siva Rajesh Jarugula (siva.rajesh.jarugula@xilinx.com)
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prasad gutti authored and saddepal committed Feb 15, 2018
1 parent 9c0a756 commit b3a4155
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30 changes: 30 additions & 0 deletions XilinxProcessorIPLib/drivers/v_sdirxss/examples/xuhdsdi_rx_example/README.txt
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/** \page example Examples

@section ex1 platform.c
This file contains low-level driver functions for Uart_16550 initialization and disabling
and enabling the caches

@section ex2 platform.h
This file contains prototypes of disabling and enabling caches.

@section ex3 platform_config.h
This file contains definitions of certain IPs like PS Uart etc.

@section ex4 si5324drv.c
This file contains low-level driver functions for controlling the SiliconLabs Si5324 clock
generator as mounted on the ZCU106 demo board

@section ex5 si5324drv.h
This file contains definitions that are being used by low-level driver functions for
controlling the SiliconLabs Si5324 clock generator as mounted on the ZCU106 demo board

@section ex6 xsdi_example.c
This file demonstrates the Xilinx SDI Rx Subsystem

@section ex7 xsdi_menu.c
This file contains the Xilinx Menu implementation as used in the SDI example design

@section ex8 xsdi_menu.h
This is the main header file for the Xilinx Menu implementation as used in the SDI example design

*/
318 changes: 318 additions & 0 deletions XilinxProcessorIPLib/drivers/v_sdirxss/examples/xuhdsdi_rx_example/lscript.ld
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A53 Linker Script */
/* */
/*******************************************************************/

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;

_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;

/* Define Memories in the system */

MEMORY
{
psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x80000000
psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
}

/* Specify the default entry point to the program */

ENTRY(_vector_table)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.text : {
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.fini (ALIGN(64)) : {
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.got1 : {
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.dtors : {
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KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
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___DTORS_END___ = .;
} > psu_ddr_0_MEM_0

.fixup : {
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.eh_frame : {
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.eh_framehdr : {
__eh_framehdr_start = .;
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.gcc_except_table : {
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.mmu_tbl0 (ALIGN(4096)) : {
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.ARM.exidx : {
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.preinit_array : {
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__preinit_array_start = .;
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} > psu_ddr_0_MEM_0

.init_array : {
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__init_array_end = .;
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.fini_array : {
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.ARM.attributes : {
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.tbss : {
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*(.bss)
*(.bss.*)
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} > psu_ddr_0_MEM_0

_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );

_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );

/* Generate Stack and Heap definitions */

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. += _HEAP_SIZE;
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. = ALIGN(64);
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_el0_stack_end = .;
. += _EL0_STACK_SIZE;
. = ALIGN(64);
__el0_stack = .;
} > psu_ddr_0_MEM_0

_end = .;
}

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