ospipsv: Added OSPI flash device reset support

This patch adds user API to do flash device reset. Currently only HW_PIN reset is supported by the API. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Acked-for-series: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Xilinx · Aug 29, 2019 · bb7fa4a · bb7fa4a
1 parent baebfe3
commit bb7fa4a
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diff --git a/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv.c b/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv.c
@@ -47,6 +47,7 @@
 *       sk   02/07/19 Added OSPI Idling sequence.
 * 1.1   sk   07/22/19 Added RX Tuning algorithm for SDR and DDR modes.
 * 1.1   mus  07/31/19 Added CCI support at EL1 NS
+*       sk   08/08/19 Added flash device reset support.
 *
 * </pre>
 *
@@ -55,6 +56,7 @@
 /***************************** Include Files *********************************/
 
 #include "xospipsv.h"
+#include "sleep.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -201,6 +203,68 @@ void XOspiPsv_Reset(const XOspiPsv *InstancePtr)
 			XOSPIPSV_DELY_DEF_VALUE);
 }
 
+/*****************************************************************************/
+/**
+*
+* This function reset the OSPI flash device.
+*
+*
+* @param	Type is Reset type.
+*
+* @return	- XST_SUCCESS if successful.
+*		- XST_FAILURE for invalid Reset Type.
+*
+* @note		None
+*
+******************************************************************************/
+u32 XOspiPsv_DeviceReset(u8 Type)
+{
+	u32 Status;
+
+	if (Type == XOSPIPSV_HWPIN_RESET) {
+#if EL1_NONSECURE
+		Xil_Smc(PIN_REQUEST_SMC_FID, PMC_GPIO_NODE_12_ID, 0, 0, 0, 0, 0, 0);
+		Xil_Smc(PIN_SET_CONFIG_SMC_FID, (((u64)PIN_CONFIG_SCHMITT_CMOS << 32) |
+				PMC_GPIO_NODE_12_ID) , 0x1, 0, 0, 0, 0, 0);
+		Xil_Smc(PIN_RELEASE_SMC_FID, PMC_GPIO_NODE_12_ID, 0, 0, 0, 0, 0, 0);
+#else
+		XOspiPsv_WriteReg(XPMC_BNK0_EN_RX_SCHMITT_HYST, 0,
+			XOspiPsv_ReadReg(XPMC_BNK0_EN_RX_SCHMITT_HYST, 0) |
+			XPMC_MIO12_MASK);
+#endif
+		XOspiPsv_WriteReg(XPMC_GPIO_DIRM, 0,
+			XOspiPsv_ReadReg(XPMC_GPIO_DIRM, 0) | XPMC_MIO12_MASK);
+		XOspiPsv_WriteReg(XPMC_GPIO_OUTEN, 0,
+			XOspiPsv_ReadReg(XPMC_GPIO_OUTEN, 0) | XPMC_MIO12_MASK);
+		XOspiPsv_WriteReg(XPMC_GPIO_DATA, 0,
+			XOspiPsv_ReadReg(XPMC_GPIO_DATA, 0) | XPMC_MIO12_MASK);
+#if EL1_NONSECURE
+		Xil_Smc(PIN_REQUEST_SMC_FID, PMC_GPIO_NODE_12_ID, 0, 0, 0, 0, 0, 0);
+		Xil_Smc(PIN_SET_CONFIG_SMC_FID, (((u64)PIN_CONFIG_TRI_STATE << 32) |
+				PMC_GPIO_NODE_12_ID) , 0, 0, 0, 0, 0, 0);
+		Xil_Smc(PIN_RELEASE_SMC_FID, PMC_GPIO_NODE_12_ID, 0, 0, 0, 0, 0, 0);
+#else
+		XOspiPsv_WriteReg(XPMC_IOU_MIO_TRI0, 0,
+			XOspiPsv_ReadReg(XPMC_IOU_MIO_TRI0, 0) & ~XPMC_MIO12_MASK);
+#endif
+		usleep(1);
+		XOspiPsv_WriteReg(XPMC_GPIO_DATA, 0,
+			XOspiPsv_ReadReg(XPMC_GPIO_DATA, 0) & ~XPMC_MIO12_MASK);
+		usleep(1);
+		XOspiPsv_WriteReg(XPMC_GPIO_DATA, 0,
+			XOspiPsv_ReadReg(XPMC_GPIO_DATA, 0) | XPMC_MIO12_MASK);
+		usleep(1);
+	} else {
+		/* TODO In-band reset */
+		Status = (u32)XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+RETURN_PATH:
+	return Status;
+}
+
 /*****************************************************************************/
 /**
 *

diff --git a/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv.h b/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv.h
@@ -47,6 +47,7 @@
 *       sk   02/07/19 Added OSPI Idling sequence.
 * 1.0   akm 03/29/19 Fixed data alignment issues on IAR compiler.
 * 1.1   sk   07/22/19 Added RX Tuning algorithm for SDR and DDR modes.
+*       sk   08/08/19 Added flash device reset support.
 *
 * </pre>
 *
@@ -229,6 +230,9 @@ typedef struct {
 #define XOSPIPSV_SDR_TX_VAL			0x5U
 #define XOSPIPSV_DDR_TX_VAL			0x0U
 
+#define XOSPIPSV_HWPIN_RESET	0x0U
+#define XOSPIPSV_INBAND_RESET	0x1U
+
 /* Initialization and reset */
 XOspiPsv_Config *XOspiPsv_LookupConfig(u16 DeviceId);
 u32 XOspiPsv_CfgInitialize(XOspiPsv *InstancePtr, const XOspiPsv_Config *ConfigPtr);
@@ -246,6 +250,7 @@ void XOspiPsv_SetStatusHandler(XOspiPsv *InstancePtr, void *CallBackRef,
 u32 XOspiPsv_SetSdrDdrMode(XOspiPsv *InstancePtr, u32 Mode);
 void XOspiPsv_ConfigureAutoPolling(XOspiPsv *InstancePtr, u32 FlashMode);
 void XOspiPsv_Idle(const XOspiPsv *InstancePtr);
+u32 XOspiPsv_DeviceReset(u8 Type);
 #ifdef __cplusplus
 }
 #endif

diff --git a/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv_hw.h b/XilinxProcessorIPLib/drivers/ospipsv/src/xospipsv_hw.h
@@ -1735,6 +1735,13 @@ extern "C" {
 #define XPMC_IOU_SLCR_OSPI_MUX_SEL		0x00000504U
 #define XPMC_IOU_SLCR_OSPI_MUX_SEL_DAC_MASK		0x00000002U
 
+#define XPMC_MIO12_MASK		0x1000U
+#define XPMC_GPIO_DIRM		0xF1020204U
+#define XPMC_GPIO_OUTEN		0xF1020208U
+#define XPMC_GPIO_DATA		0xF1020040U
+#define XPMC_BNK0_EN_RX_SCHMITT_HYST	0xF106010CU
+#define XPMC_IOU_MIO_TRI0				0xF1060200U
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_smc.h b/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_smc.h
@@ -71,9 +71,15 @@ extern "C" {
 
 #define PM_IOCTL_SMC_FID	0xC2000022U
 #define PM_IOCTL_OSPI_MUX_SELECT	0x15U
+#define PIN_CONFIG_SCHMITT_CMOS		0x3U
+#define PIN_CONFIG_TRI_STATE		0x6U
 #define PM_OSPI_MUX_SEL_DMA		0x0
 #define PM_OSPI_MUX_SEL_LINEAR	0x1
 #define OSPI_NODE_ID	0x1822402a
+#define PMC_GPIO_NODE_12_ID		0x14108027
+#define PIN_REQUEST_SMC_FID		0xC200001CU
+#define PIN_RELEASE_SMC_FID		0xC200001DU
+#define PIN_SET_CONFIG_SMC_FID		0xC2000021U
 #define PM_REQUEST_DEVICE_SMC_FID	0xC200000DU
 #define PM_RELEASE_DEVICE_SMC_FID	0xC200000EU
 #define PM_ASSERT_SMC_FID       0xC2000011U